8.5.1.1 I²C Control Mode

The TLV320ADC3100 supports the I²C control protocol and is capable of both standard and fast modes. Standard mode is up to 100 kHz and fast mode is up to 400 kHz. When in I²C control mode, the TLV320ADC3100 can be configured for one of four different addresses, using the I2C_ADR1 and I2C_ADR0 pins, which control the two LSBs of the device address. The five MSBs of the device address are fixed as 0011 0 and cannot be changed, whereas the two LSBs are given by I2C_ADR1:I2C_ADR0. Table 14 lists the four possible device addresses resulting from this configuration.

I²C is a two-wire, open-drain interface supporting multiple devices and masters on a single bus. Devices on the I²C bus only drive the bus lines low by connecting them to ground; they never drive the bus lines high. Instead, the bus wires are pulled high by pullup resistors, so the bus wires are high when no device is driving them low. This way, two devices cannot conflict; if two devices drive the bus simultaneously, there is no driver contention.

Communication on the I²C bus always takes place between two devices, one acting as the master and the other acting as the slave. Both masters and slaves can read and write, but slaves can only do so under the direction of the master. Some I²C devices can act as masters or slaves, but the TLV320ADC3100 can only act as a slave device.

An I²C bus consists of two lines, SDA and SCL. SDA carries data; SCL provides the clock. All data are transmitted across the I²C bus in groups of eight bits. To send a bit on the I²C bus, the SDA line is driven to the appropriate level when SCL is low (a low on SDA indicates the bit is 0; a high indicates the bit is 1). When the SDA line has settled, the SCL line is brought high, then low. This pulse on SCL clocks the SDA bit into the receiver shift register.

The I²C bus is bidirectional: the SDA line is used both for transmitting and receiving data. When a master reads from a slave, the slave drives the data line; when a master sends to a slave, the master drives the data line. Under normal circumstances, the master drives the clock line.

Most of the time the bus is idle, no communication is taking place, and both lines are high. When communication is taking place, the bus is active. Only master devices can start a communication by causing a START condition on the bus. Normally, the data line is only allowed to change state when the clock line is low. If the data line changes state when the clock line is high, the state is either a START condition or its counterpart, a STOP condition. A START condition is when the clock line is high and the data line goes from high to low. A STOP condition is when the clock line is high and the data line goes from low to high.

After the master issues a START condition, the master sends a byte indicating the slave device to communicate with. This byte is called the address byte. Each device on an I²C bus has a unique 7-bit address that is used to respond with. (Slaves can also have 10-bit addresses; see the I²C specification for details.) The master sends an address in the address byte, together with a bit that indicates whether the slave device is to be read from or written to.

Every byte transmitted on the I²C bus, whether address or data, is acknowledged with an acknowledge bit. When a master has finished sending a byte (eight data bits) to a slave, the master stops driving SDA and waits for the slave to acknowledge the byte. The slave acknowledges the byte by pulling SDA low. The master then sends a clock pulse to clock the acknowledge bit. Similarly, when a master has finished reading a byte, the master pulls SDA low to acknowledge this read to the slave. The master then sends a clock pulse to clock the bit.

A not-acknowledge is performed by leaving SDA high during an acknowledge cycle. If the master attempts to address a device not present on the bus, then the master receives a not-acknowledge because no device is present at that address to pull the line low.

When a master has finished communicating with a slave, the master may issue a STOP condition. When a STOP condition is issued, the bus becomes idle again. A master may also issue another START condition. If a START condition is issued when the bus is active, this condition is called a repeated START condition.

The TLV320ADC3100 also responds to and acknowledges a general call, which consists of the master issuing a command with a slave address byte of 00h. Figure 43 and Figure 44 show timing diagrams for I²C write and read operations, respectively.

Figure 43. I²C Write

Figure 44. I²C Read

In the case of an I²C register write, if the master does not issue a STOP condition, then the device enters auto-increment mode. So in the next eight clocks, the data on SDA are treated as the data for the next incremental register.

Similarly, after the device has transmitted the 8-bit data from the addressed register for an I²C register read, and if the master issues an acknowledge, the slave then takes control of the SDA bus and transmits the next eight clocks of data for the next incremental register.