SLAS553B November   2008  – August 2015 TLV320ADC3101

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  Electrical Characteristics
    6. 8.6  Dissipation Ratings
    7. 8.7  I2S/LJF/RJF Timing in Master Mode
    8. 8.8  DSP Timing in Master Mode
    9. 8.9  I2S/LJF/RJF Timing in Slave Mode
    10. 8.10 DSP Timing in Slave Mode
    11. 8.11 Typical Characteristics
  9. 9 Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1  Hardware Reset
      2. 10.3.2  PLL Start-up
      3. 10.3.3  Software Power Down
      4. 10.3.4  miniDSP
      5. 10.3.5  Audio Data Converters
      6. 10.3.6  Digital Audio Data Serial Interface
        1. 10.3.6.1 Right-Justified Mode
        2. 10.3.6.2 Left-Justified Mode
        3. 10.3.6.3 I2S Mode
        4. 10.3.6.4 DSP Mode
      7. 10.3.7  Audio Clock Generation
      8. 10.3.8  Stereo Audio ADC
      9. 10.3.9  Audio Analog Inputs
        1. 10.3.9.1 Digital Volume Control
        2. 10.3.9.2 Fine Digital Gain Adjustment
        3. 10.3.9.3 AGC
      10. 10.3.10 Input Impedance and VCM Control
      11. 10.3.11 MICBIAS Generation
      12. 10.3.12 ADC Decimation Filtering and Signal Processing
        1. 10.3.12.1 Processing Blocks
        2. 10.3.12.2 Processing Blocks - Details
          1. 10.3.12.2.1 First-Order IIR, AGC, Filter A
          2. 10.3.12.2.2 Five Biquads, First-Order IIR, AGC, Filter A
          3. 10.3.12.2.3 25-Tap FIR, First-Order IIR, AGC, Filter A
          4. 10.3.12.2.4 First-Order IIR, AGC, Filter B
          5. 10.3.12.2.5 Three Biquads, First-Order IIR, AGC, Filter B
          6. 10.3.12.2.6 20-Tap FIR, First-Order IIR, AGC, Filter B
          7. 10.3.12.2.7 First-Order IIR, AGC, Filter C
          8. 10.3.12.2.8 Five Biquads, First-Order IIR, AGC, Filter C
          9. 10.3.12.2.9 25-Tap FIR, First-Order IIR, AGC, Filter C
        3. 10.3.12.3 User-Programmable Filters
          1. 10.3.12.3.1 First-Order IIR Section
          2. 10.3.12.3.2 Biquad Section
          3. 10.3.12.3.3 FIR Section
        4. 10.3.12.4 Decimation Filter
          1. 10.3.12.4.1 Decimation Filter A
          2. 10.3.12.4.2 Decimation Filter B
          3. 10.3.12.4.3 Decimation Filter C
        5. 10.3.12.5 ADC Data Interface
        6. 10.3.12.6 Digital Microphone Function
    4. 10.4 Device Functional Modes
      1. 10.4.1 Recording Mode
    5. 10.5 Programming
      1. 10.5.1 Digital Control Serial Interface
        1. 10.5.1.1 I2C Control Mode
    6. 10.6 Register Maps
      1. 10.6.1 Control Registers
      2. 10.6.2 Control Registers, Page 0: Clock Multipliers and Dividers, Serial Interfaces, Flags, Interrupts and Programming of GPIOs
      3. 10.6.3 CONTROL REGISTERS Page 1: ADC Routing, PGA, Power-Controls, Etc.
      4. 10.6.4 Control Registers, Page 4: ADC Digital Filter Coefficients
      5. 10.6.5 Control Registers, Page 5: ADC Programmable Coefficients RAM (65:127)
      6. 10.6.6 Control Registers, Page 32: ADC DSP Engine Instruction RAM (0:31)
        1. 10.6.6.1 Page 32 / Register 5 Through Page 32 / Register 97
      7. 10.6.7 Control Registers, Pages 33-47: ADC DSP Engine Instruction RAM (32:63) Through (480:511)
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Application
      1. 11.2.1 Design Requirements
      2. 11.2.2 Detailed Design Procedure
        1. 11.2.2.1 Step 1
        2. 11.2.2.2 Step 2
        3. 11.2.2.3 Example Register Setup to Record Analog Data Through ADC to Digital Out
        4. 11.2.2.4 MICBIAS
        5. 11.2.2.5 Decoupling Capacitors
      3. 11.2.3 Application Curves
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Example
  14. 14Device and Documentation Support
    1. 14.1 Community Resources
    2. 14.2 Trademarks
    3. 14.3 Electrostatic Discharge Caution
    4. 14.4 Glossary
  15. 15Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7 Pin Configuration and Functions

RGE Package
24-Pin VQFN With Exposed Thermal Pad
Top View
TLV320ADC3101 rge-24_po_las553.gif
Connect the VQFN thermal pad to AVSS.

Pin Functions

PIN TYPE DESCRIPTION
NAME NO.
AVDD 10 P Analog voltage supply, 2.6 V–3.6 V
AVSS 9 P Analog ground supply, 0 V
BCLK 1 I/O Audio serial data bus bit clock (input/output)
DMCLK/GPIO2 20 I/O Digital microphone clock / general-purpose input/output 2 (input/output) / PLL clock input / audio serial data-bus bit-clock input/output / multifunction pin based on register programming
DMDIN/GPIO1 19 I/O Digital microphone data input / general-purpose input/output 1 (input/output) / PLL clock mux output / AGC noise flag / multifunction pin based on register programming
DOUT 3 O Audio serial data bus data output (output)
DVDD 22 P Digital core voltage supply, 1.65 V–1.95 V
DVSS 23 P Digital ground supply, 0 V
I2C_ADR0 15 I LSB of I2C bus address
I2C_ADR1 16 I LSB + 1 of I2C bus address
IN1L(P) 8 I Mic or line analog input (left-channel single-ended or differential plus, or right channel)
IN1R(M) 11 I Mic or line analog input (left-channel single-ended or differential minus, or left channel)
IN2L(P) 7 I Mic or line analog input (left-channel single-ended or differential plus)
IN2R(P) 12 I Mic or line analog input (right-channel single-ended or differential plus)
IN3L(M) 6 I Mic or line analog input (left-channel single-ended or differential minus)
IN3R(M) 13 I Mic or line analog input (right-channel single-ended or differential minus)
IOVDD 21 P I/O voltage supply, 1.1 V–3.6 V
MCLK 24 I Master clock input
MICBIAS1 5 O MICBIAS1 bias voltage output
MICBIAS2 14 O MICBIAS2 bias voltage output
RESET 4 I Reset
SCL 17 I/O I2C serial clock
SDA 18 I/O I2C serial data input/output
WCLK 2 I/O Audio serial data bus word clock (input/output)
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