SLAS520E February   2007  – December 2014 TLV320AIC3101

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Diagram
  5. 5 Revision History
  6. 6 Description (continued)
  7. 7 Device Comparison Table
  8. 8 Pin Configuration and Functions
  9. 9 Specifications
    1. 9.1 Absolute Maximum Ratings
    2. 9.2 ESD Ratings
    3. 9.3 Recommended Operating Conditions
    4. 9.4 Thermal Information
    5. 9.5 Electrical Characteristics
    6. 9.6 Timing Requirements: Audio Data Serial Interface
    7. 9.7 Typical Characteristics
  10. 10Parameter Measurement Information
  11. 11Detailed Description
    1. 11.1 Overview
    2. 11.2 Functional Block Diagram
    3. 11.3 Feature Description
      1. 11.3.1  Hardware Reset
      2. 11.3.2  Digital Audio Data Serial Interface
        1. 11.3.2.1 Right-Justified Mode
        2. 11.3.2.2 Left-Justified Mode
        3. 11.3.2.3 I2S Mode
        4. 11.3.2.4 DSP Mode
        5. 11.3.2.5 TDM Data Transfer
      3. 11.3.3  Audio Data Converters
        1. 11.3.3.1 Audio Clock Generation
        2. 11.3.3.2 Stereo Audio ADC
          1. 11.3.3.2.1 Stereo Audio ADC High-Pass Filter
          2. 11.3.3.2.2 Automatic Gain Control (AGC)
            1. 11.3.3.2.2.1 Target Level
            2. 11.3.3.2.2.2 Attack Time
            3. 11.3.3.2.2.3 Decay Time
            4. 11.3.3.2.2.4 Noise Gate Threshold
            5. 11.3.3.2.2.5 Maximum PGA Gain Applicable
        3. 11.3.3.3 Stereo Audio DAC
          1. 11.3.3.3.1 Digital Audio Processing for Playback
          2. 11.3.3.3.2 Digital Interpolation Filter
          3. 11.3.3.3.3 Audio DAC Digital Volume Control
          4. 11.3.3.3.4 Increasing DAC Dynamic Range
          5. 11.3.3.3.5 Analog Output Common-Mode Adjustment
          6. 11.3.3.3.6 Audio DAC Power Control
      4. 11.3.4  Audio Analog Inputs
      5. 11.3.5  Analog Fully Differential Line Output Drivers
      6. 11.3.6  Analog High-Power Output Drivers
      7. 11.3.7  Input Impedance and VCM Control
      8. 11.3.8  MICBIAS Generation
      9. 11.3.9  Short-Circuit Output Protection
      10. 11.3.10 Jack/Headset Detection
    4. 11.4 Device Functional Modes
      1. 11.4.1 Bypass Path Mode
        1. 11.4.1.1 Analog Input Bypass Path Functionality
        2. 11.4.1.2 ADC PGA Signal Bypass Path Functionality
        3. 11.4.1.3 Passive Analog Bypass During Power Down
      2. 11.4.2 Digital Audio Processing for Record Path
    5. 11.5 Programming
      1. 11.5.1 I2C Control Interface
      2. 11.5.2 I2C Bus Debug in a Glitched System
    6. 11.6 Register Maps
    7. 11.7 Output Stage Volume Controls
  12. 12Application and Implementation
    1. 12.1 Application Information
    2. 12.2 Typical Application
      1. 12.2.1 AC-Coupled Headphone Output With Separate Line Outputs and External Speaker Amplifier
        1. 12.2.1.1 Design Requirements
        2. 12.2.1.2 Detailed Design Procedure
        3. 12.2.1.3 Application Curves
      2. 12.2.2 Connections With Headphone and External Speaker Driver in Cell Phone Application
        1. 12.2.2.1 Design Requirements
        2. 12.2.2.2 Detailed Design Procedure
        3. 12.2.2.3 Application Curves
  13. 13Power Supply Recommendations
  14. 14Layout
    1. 14.1 Layout Guidelines
    2. 14.2 Layout Example
  15. 15Device and Documentation Support
    1. 15.1 Trademarks
    2. 15.2 Electrostatic Discharge Caution
    3. 15.3 Glossary
  16. 16Mechanical, Packaging, and Orderable Information

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12 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

12.1 Application Information

The TLV320AIC3101 is a highly integrated low-power stereo audio codec with integrated stereo speaker/headphone/ line amplifier, as well as multiple inputs and outputs that are programmable in single-ended or fully differential configurations. Pairs of high power drivers can be used to drive 8-Ω speakers in BTL configuration. All the features of the TLV320AIC3101 are accessed by programmable registers. External processor with I2C protocol is required to control the device. It is good practice to perform a hardware reset after initial power up to ensure that all registers are in their default states. Extensive register-based power control is included, enabling stereo 48-kHz DAC playback as low as 14-mW from a 3.3-V analog supply, making it ideal for portable battery-powered audio and telephony applications.

12.2 Typical Application

12.2.1 AC-Coupled Headphone Output With Separate Line Outputs and External Speaker Amplifier

TLV320AIC3101 is a versatile device capable of being configured in several ways suited for portable applications. This device could be configured to have two microphones with an FM tuner connected to the analog inputs. High power driver outputs can drive an external power amplifier and headphone, and still have a fully differential stereo line output.

s0207-02_las520.gifFigure 33. Typical Connections for AC-Coupled Headphone Output With Separate Line Outputs and External Speaker Amplifier

12.2.1.1 Design Requirements

For this design example, use the parameters shown in Table 180.

Table 180. Design Parameters

PARAMETER VALUE
Supply Voltage (AVDD, DRVDD) 3.3 V
Supply Voltage (DVDD, IOVDD) 1.8 V
Analog High-Power Output Driver load 16 Ω
Analog Fully Differential Line Output Driver load 10 kΩ

12.2.1.2 Detailed Design Procedure

Using the Typical Application Schematic as a guide, integrate the hardware into the system.

Following the recommended component placement, schematic layout and routing given in the Layout Example section, integrate the device and its supporting components into the system PCB file.

  • For questions and support go to the E2E forums (e2e.ti.com). If it is necessary to deviate from the recommended layout, visit the E2E forum to request a layout review.

Determining sample rate and Master clock frequency is required since powering up the device as all internal timing is derived from the master clock. Refer to the Figure 17 in order to get more information of how to configure correctly the required clocks for the device.

As the TLV320AIC3101 is designed for low-power applications, when powered up, the device has several features powered down. A correct routing of the TLV320AIC3101 signals is achieved by a correct setting of the device registers, powering up the required stages of the device and configuring the internal switches to follow a desired route.

For more information of the device configuration and programming, refer to the TLV320AIC3101 technical documents section in ti.com (http://www.ti.com/product/TLV320AIC3101/technicaldocuments).

12.2.1.3 Application Curves

g001_las520.gif
Figure 34. THD vs Headphone Power, AC-Coupled
g005_las520.gif
Figure 36. THD vs Speaker Power, 8 Ω Load
g002_las520.gif
Figure 35. THD vs Headphone Power, Capless

12.2.2 Connections With Headphone and External Speaker Driver in Cell Phone Application

s0206-02_las520.gifFigure 37. Typical Connections With Headphone and External Speaker Driver in Cell Phone Application

12.2.2.1 Design Requirements

See Analog Fully Differential Line Output Drivers section for the design requirements.

12.2.2.2 Detailed Design Procedure

See Analog Fully Differential Line Output Drivers section for the design requirements.

12.2.2.3 Application Curves

See Analog Fully Differential Line Output Drivers section for the application curves.
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