SLAS663C August   2009  – June 2016 TLV320AIC3106-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (Continued)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  Electrical Characteristics
    6. 8.6  Switching Characteristics I2S/LJF/RJF In Master Mode
    7. 8.7  Switching Characteristics I2S/LJF/RJF In Slave Mode
    8. 8.8  Switching Characteristics DSP In Master Mode
    9. 8.9  Switching Characteristics DSP In Slave Mode
    10. 8.10 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Audio Data Converters
      2. 9.3.2  Stereo Audio ADC
        1. 9.3.2.1 Stereo Audio ADC High-Pass Filter
      3. 9.3.3  Automatic Gain Control (AGC)
      4. 9.3.4  Stereo Audio DAC
      5. 9.3.5  Digital Audio Processing For Playback
      6. 9.3.6  Digital Interpolation Filter
      7. 9.3.7  Delta-Sigma Audio Dac
      8. 9.3.8  Audio Dac Digital Volume Control
      9. 9.3.9  Analog Output Common-Mode Adjustment
      10. 9.3.10 Audio DAC Power Control
      11. 9.3.11 Audio Analog Inputs
      12. 9.3.12 Analog Input Bypass Path Functionality
      13. 9.3.13 ADC PGA Signal Bypass Path Functionality
      14. 9.3.14 Input Impedance and VCM Control
      15. 9.3.15 MICBIAS Generation
      16. 9.3.16 Analog Fully Differential Line Output Drivers
      17. 9.3.17 Analog High Power Output Drivers
      18. 9.3.18 Short Circuit Output Protection
      19. 9.3.19 Jack and Headset Detection
      20. 9.3.20 General-Purpose I/O
    4. 9.4 Device Functional Modes
      1. 9.4.1 Digital Audio Processing For Record Path
      2. 9.4.2 Increasing DAC Dynamic Range
      3. 9.4.3 Passive Analog Bypass During Powerdown
      4. 9.4.4 Digital Microphone Connectivity
    5. 9.5 Programming
      1. 9.5.1  Hardware Reset
      2. 9.5.2  Digital Control Serial Interface
        1. 9.5.2.1 SPI Control Mode
        2. 9.5.2.2 SPI Communication Protocol
          1. 9.5.2.2.1 Limitation On Register Writing
        3. 9.5.2.3 Continuous Read and Write Operation
      3. 9.5.3  I2C Control Mode
      4. 9.5.4  I2C Bus Debug In A Glitched System
      5. 9.5.5  Digital Audio Data Serial Interface
      6. 9.5.6  Right-Justified Mode
      7. 9.5.7  Left-Justified Mode
      8. 9.5.8  I2S Mode
      9. 9.5.9  DSP Mode
      10. 9.5.10 TDM Data Transfer
      11. 9.5.11 Audio Clock Generation
    6. 9.6 Register Maps
      1. 9.6.1 Output Stage Volume Controls
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Receiving Notification of Documentation Updates
    2. 13.2 Community Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, And Orderable Information

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14 Mechanical, Packaging, And Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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