7.3.7 Analog High-Power Output Drivers

The TLV320AIC3109-Q1 includes two high-power output drivers with extensive flexibility in their usage. These output drivers are individually capable of driving 30 mW each into a 16-Ω load in single-ended configuration, and can be used in pairs connected in a bridge-terminated load (BTL) configuration between two driver outputs.

The high-power output drivers can be configured in a variety of ways, including:

1. Driving up to two single-ended output signals
2. Driving one single-ended output signal, with the remaining driver driving a fixed VCM level

The output stage architecture leading to the high-power output drivers is provided in Figure 23, with the volume control and mixing blocks being effectively identical to those in Figure 22. Each of these drivers has an output level control block like those included with the line output drivers, allowing gain adjustment up to 9 dB on the output signal. As in the previous case, this output level adjustment is not intended to be used as a standard volume control, but instead is included for additional full-scale output signal-level control.

Figure 23. Architecture of the Output Stage Leading to the High-Power Output Drivers

The high-power output drivers include additional circuitry to avoid artifacts on the audio output during power-on and power-off transient conditions. First program the type of output configuration being used in register 14, page 0 to allow the device to select the optimal power-up scheme to avoid output artifacts. The power-up delay time for the high-power output drivers is also programmable over a wide range of time delays, from instantaneous up to 4 s, using register 42, page 0.

When powered down, place these output drivers into a variety of output conditions based on register programming. If lowest-power operation is desired, then the outputs can be placed into a high-impedance state and all power to the output stage is removed. However, this generally results in the output nodes drifting to rest near the upper or lower analog supply because of small leakage currents at the pins, which then results in a longer delay requirement to avoid output artifacts during driver power-on. In order to reduce this required power-on delay, the TLV320AIC3109-Q1 includes an option for the output pins of the drivers to be weakly driven to the VCM level that the pins normally rest at when powered with no signal applied. This output VCM level is determined by an internal band-gap voltage reference, and thus results in extra power dissipation when the drivers are in power down. However, this option provides the fastest method for transitioning the drivers from power-down to full-power operation without any output artifact introduced.

The device includes a further option that falls between the other two—although less power is required when the output drivers are in power down, a slightly longer delay is required to power up without artifacts than if the band-gap reference is kept alive. In this alternate mode, the powered-down output driver pin is weakly driven to a voltage of approximately half the DRVDD supply level using an internal voltage divider. This voltage does not match the actual VCM of a fully powered driver, but because of the output voltage being close to the final value, a much shorter power-up delay time setting can be used and still avoid any audible output artifacts. These output voltage options are controlled in page 0, register 42.

The high-power output drivers can also be programmed to power up first with the output level (gain) control in a highly attenuated state; then the output driver automatically reduces the output attenuation slowly to reach the programmed output gain. This capability is enabled by default but can be enabled in register 40, page 0.