SLAS647C December   2009  – May 2016 TLV320AIC3110

PRODUCTION DATA.  

  1. 1 Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2 Revision History
  3. 3  Device Comparison
  4. 4 Pin Configuration and Functions
    1. 4.1 Pin Attributes
  5. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Power Dissipation Ratings
    7. 5.7  I2S, LJF, and RJF Timing in Master Mode
    8. 5.8  I2S, LJF, and RJF Timing in Slave Mode
    9. 5.9  DSP Timing in Master Mode
    10. 5.10 DSP Timing in Slave Mode
    11. 5.11 I2C Interface Timing
    12. 5.12 Typical Characteristics
      1. 5.12.1 Audio ADC Performance
      2. 5.12.2 DAC Performance
      3. 5.12.3 Class-D Speaker Driver Performance
      4. 5.12.4 Analog Bypass Performance H
      5. 5.12.5 MICBIAS Performance H
  6. 6 Parameter Measurement Information
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Power-Supply Sequence
      2. 7.3.2  Reset
      3. 7.3.3  Device Start-Up Lockout Times
      4. 7.3.4  PLL Start-Up
      5. 7.3.5  Power-Stage Reset
      6. 7.3.6  Software Power Down
      7. 7.3.7  Audio Analog I/O
      8. 7.3.8  Digital Processing Low-Power Modes
        1. 7.3.8.1 ADC, Mono, 48 kHz, DVDD = 1.8 V, AVDD = 3.3 V
        2. 7.3.8.2 ADC, Mono, 8 kHz, DVDD = 1.8 V, AVDD = 3.3 V
        3. 7.3.8.3 DAC Playback on Headphones, Stereo, 48 kHz, DVDD = 1.8 V, AVDD = 3.3 V, HPVDD = 3.3 V
        4. 7.3.8.4 DAC Playback on Headphones, Mono, 48 kHz, DVDD = 1.8 V, AVDD = 3.3 V, HPVDD = 3.3 V
        5. 7.3.8.5 DAC Playback on Headphones, Stereo, 8 kHz, DVDD = 1.8 V, AVDD = 3.3 V, HPVDD = 3.3 V
        6. 7.3.8.6 DAC Playback on Headphones, Mono, 8 kHz, DVDD = 1.8 V, AVDD = 3.3 V, HPVDD = 3.3 V
        7. 7.3.8.7 DAC Playback on Headphones, Stereo, 192 kHz, DVDD = 1.8 V, AVDD = 3.3 V, HPVDD = 3.3 V
        8. 7.3.8.8 DAC Playback on Line Out (10 k-Ω load), Stereo, 48 kHz, DVDD = 1.8 V, AVDD = 3 V, HPVDD = 3 V
      9. 7.3.9  Audio ADC and Analog Inputs
        1. 7.3.9.1 MICBIAS and Microphone Preamplifier
        2. 7.3.9.2 Automatic Gain Control (AGC)
        3. 7.3.9.3 Delta-Sigma ADC
        4. 7.3.9.4 ADC Decimation Filtering and Signal Processing
          1. 7.3.9.4.1 ADC Processing Blocks
          2. 7.3.9.4.2 ADC Processing Blocks - Signal Chain Details
            1. 7.3.9.4.2.1 First-Order IIR, AGC, Filter A
            2. 7.3.9.4.2.2 Five Biquads, First-Order IIR, AGC, Filter A
            3. 7.3.9.4.2.3 25-Tap FIR, First-Order IIR, AGC, Filter A
            4. 7.3.9.4.2.4 First-Order IIR, AGC, Filter B
            5. 7.3.9.4.2.5 Three Biquads, First-Order IIR, AGC, Filter B
            6. 7.3.9.4.2.6 20-Tap FIR, First-Order IIR, AGC, Filter B
            7. 7.3.9.4.2.7 First-Order IIR, AGC, Filter C
            8. 7.3.9.4.2.8 Five Biquads, First-Order IIR, AGC, Filter C
            9. 7.3.9.4.2.9 25-Tap FIR, First-Order IIR, AGC, Filter C
          3. 7.3.9.4.3 User-Programmable Filters
            1. 7.3.9.4.3.1 First-Order IIR Section
            2. 7.3.9.4.3.2 Biquad Section
            3. 7.3.9.4.3.3 FIR Section
          4. 7.3.9.4.4 ADC Digital Decimation Filter Characteristics
            1. 7.3.9.4.4.1 Decimation Filter A
            2. 7.3.9.4.4.2 Decimation Filter B
            3. 7.3.9.4.4.3 Decimation Filter C
          5. 7.3.9.4.5 ADC Data Interface
        5. 7.3.9.5 Updating ADC Digital Filter Coefficients During Record
        6. 7.3.9.6 Digital Microphone Function
        7. 7.3.9.7 DC Measurement
      10. 7.3.10 Audio DAC and Audio Analog Outputs
        1. 7.3.10.1  DAC
          1. 7.3.10.1.1 DAC Processing Blocks
          2. 7.3.10.1.2 DAC Processing Blocks — Details
            1. 7.3.10.1.2.1  Three Biquads, Filter A
            2. 7.3.10.1.2.2  Six Biquads, First-Order IIR, DRC, Filter A or B
            3. 7.3.10.1.2.3  Six Biquads, First-Order IIR, Filter A or B
            4. 7.3.10.1.2.4  IIR, Filter B or C
            5. 7.3.10.1.2.5  Four Biquads, DRC, Filter B
            6. 7.3.10.1.2.6  Four Biquads, Filter B
            7. 7.3.10.1.2.7  Four Biquads, First-Order IIR, DRC, Filter C
            8. 7.3.10.1.2.8  Four Biquads, First-Order IIR, Filter C
            9. 7.3.10.1.2.9  Two Biquads, 3D, Filter A
            10. 7.3.10.1.2.10 Five Biquads, DRC, 3D, Filter A
            11. 7.3.10.1.2.11 Five Biquads, DRC, 3D, Beep Generator, Filter A
          3. 7.3.10.1.3 DAC User-Programmable Filters
            1. 7.3.10.1.3.1 First-Order IIR Section
            2. 7.3.10.1.3.2 Biquad Section
          4. 7.3.10.1.4 DAC Interpolation Filter Characteristics
            1. 7.3.10.1.4.1 Interpolation Filter A
            2. 7.3.10.1.4.2 Interpolation Filter B
            3. 7.3.10.1.4.3 Interpolation Filter C
        2. 7.3.10.2  DAC Digital-Volume Control
        3. 7.3.10.3  Volume Control Pin
        4. 7.3.10.4  Dynamic Range Compression
          1. 7.3.10.4.1 DRC Threshold
          2. 7.3.10.4.2 DRC Hysteresis
          3. 7.3.10.4.3 DRC Hold Time
          4. 7.3.10.4.4 DRC Attack Rate
          5. 7.3.10.4.5 DRC Decay Rate
          6. 7.3.10.4.6 Example Setup for DRC
        5. 7.3.10.5  Headset Detection
        6. 7.3.10.6  Interrupts
        7. 7.3.10.7  Key-Click Functionality With Digital Sine-Wave Generator (PRB_P25)
        8. 7.3.10.8  Programming DAC Digital Filter Coefficients
        9. 7.3.10.9  Updating DAC Digital Filter Coefficients During PLAY
        10. 7.3.10.10 Digital Mixing and Routing
        11. 7.3.10.11 Analog Audio Routing
          1. 7.3.10.11.1 Analog Output Volume Control
          2. 7.3.10.11.2 Headphone Analog-Output Volume Control
          3. 7.3.10.11.3 Class-D Speaker Analog Output Volume Control
        12. 7.3.10.12 Analog Outputs
          1. 7.3.10.12.1 Headphone Drivers
          2. 7.3.10.12.2 Speaker Drivers
        13. 7.3.10.13 Audio-Output Stage-Power Configurations
        14. 7.3.10.14 Example Register Setup to Play Digital Data Through DAC and Headphone/Speaker Outputs
      11. 7.3.11 CLOCK Generation and PLL
        1. 7.3.11.1 PLL
      12. 7.3.12 Timer
      13. 7.3.13 Digital Audio and Control Interface
        1. 7.3.13.1 Digital Audio Interface
          1. 7.3.13.1.1 Right-Justified Mode
          2. 7.3.13.1.2 Left-Justified Mode
          3. 7.3.13.1.3 I2S Mode
          4. 7.3.13.1.4 DSP Mode
        2. 7.3.13.2 Primary and Secondary Digital Audio Interface Selection
        3. 7.3.13.3 Control Interface
          1. 7.3.13.3.1 I2C Control Mode
    4. 7.4 Register Map
      1. 7.4.1 TLV320AIC3110 Register Map
      2. 7.4.2 Registers
        1. 7.4.2.1 Control Registers, Page 0 (Default Page): Clock Multipliers, Dividers, Serial Interfaces, Flags, Interrupts, and GPIOs
        2. 7.4.2.2 Control Registers, Page 1: DAC and ADC Routing, PGA, Power-Controls, and MISC Logic-Related Programmability
        3. 7.4.2.3 Control Registers, Page 3: MCLK Divider for Programmable Delay Timer
        4. 7.4.2.4 Control Registers, Page 4: ADC Digital Filter Coefficients
        5. 7.4.2.5 Control Registers, Page 8: DAC Digital Filter Coefficients
        6. 7.4.2.6 Control Registers, Page 9: DAC Digital Filter Coefficients
        7. 7.4.2.7 Control Registers, Page 12: DAC Programmable Coefficients Buffer B (1:63)
        8. 7.4.2.8 Control Registers, Page 13: DAC Programmable Coefficients RAM Buffer B (65:127)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Community Resources
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical Packaging and Orderable Information
    1. 12.1 Packaging Information

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10 Layout

10.1 Layout Guidelines

PCB design is made considering the application and the review is specific for each system requirements. However, general considerations can optimize the system performance.

  • The TLV320AIC3110 thermal pad must be connected to analog output driver ground using multiple VIAS to minimize impedance between the device and ground.
  • Analog and digital grounds must be separated to prevent possible digital noise form affecting the analog performance of the board.
  • The TLV320AIC3110 requires the decoupling capacitors to be placed as close as possible to the device power supply terminals.

10.2 Layout Example

TLV320AIC3110 layout_example_slas667.gif Figure 10-1 Example PCB Layout
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