ZHCSJS1E September   2008  – September 2019 TLV320AIC3204

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 描述
    1.     Device Images
      1.      简化方框图
  4. 4 修订历史记录
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics, ADC
    6. 7.6  Electrical Characteristics, Bypass Outputs
    7. 7.7  Electrical Characteristics, Microphone Interface
    8. 7.8  Electrical Characteristics, Audio DAC Outputs
    9. 7.9  Electrical Characteristics, LDO
    10. 7.10 Electrical Characteristics, Misc.
    11. 7.11 Electrical Characteristics, Logic Levels
    12. 7.12 I2S LJF and RJF Timing in Master Mode (see )
    13. 7.13 I2S LJF and RJF Timing in Slave Mode (see )
    14. 7.14 DSP Timing in Master Mode (see )
    15. 7.15 DSP Timing in Slave Mode (see )
    16. 7.16 Digital Microphone PDM Timing (see )
    17. 7.17 I2C Interface Timing
    18. 7.18 SPI Interface Timing (See )
    19. 7.19 Typical Characteristics
    20. 7.20 Typical Characteristics, FFT
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Device Connections
        1. 9.3.1.1 Digital Pins
          1. 9.3.1.1.1 Multifunction Pins
        2. 9.3.1.2 Analog Pins
      2. 9.3.2 Analog Audio IO
        1. 9.3.2.1 Analog Low Power Bypass
        2. 9.3.2.2 ADC Bypass Using Mixer Amplifiers
        3. 9.3.2.3 Headphone Outputs
        4. 9.3.2.4 Line Outputs
      3. 9.3.3 ADC
        1. 9.3.3.1 ADC Processing
          1. 9.3.3.1.1 ADC Processing Blocks
      4. 9.3.4 DAC
        1. 9.3.4.1 DAC Processing Blocks
      5. 9.3.5 PowerTune
      6. 9.3.6 Digital Audio IO Interface
      7. 9.3.7 Clock Generation and PLL
      8. 9.3.8 Control Interfaces
        1. 9.3.8.1 I2C Control
        2. 9.3.8.2 SPI Control
    4. 9.4 Device Functional Modes
    5. 9.5 Register Map
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
        1. 10.2.1.1 Reference Filtering Capacitor
        2. 10.2.1.2 MICBIAS
      2. 10.2.2 Detailed Design Procedures
        1. 10.2.2.1 Analog Input Connection
        2. 10.2.2.2 Analog Output Connection
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13器件和文档支持
    1. 13.1 文档支持
      1. 13.1.1 相关文档
    2. 13.2 接收文档更新通知
    3. 13.3 社区资源
    4. 13.4 商标
    5. 13.5 静电放电警告
    6. 13.6 Glossary
  14. 14机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.3 Recommended Operating Conditions

MIN NOM MAX UNIT
LDOIN Power Supply Voltage Range Referenced to AVSS(1) 1.9 3.6 V
AVDD 1.5 1.8 1.95
IOVDD Referenced to IOVSS(1) 1.1 3.6
DVDD(2) Referenced to DVSS(1) 1.26 1.8 1.95
PLL Input Frequency Clock divider uses fractional divide
(D > 0), P = 1, DVDD ≥ 1.65V (Refer to the table in SLAA557, Maximum TLV320AIC3204 Clock Frequencies) 		10 20 MHz
Clock divider uses integer divide
(D = 0), P = 1, DVDD ≥ 1.65V (Refer to the table in SLAA557, Maximum TLV320AIC3204 Clock Frequencies) 		0.512 20 MHz
MCLK Master Clock Frequency MCLK; Master Clock Frequency; DVDD ≥ 1.65V 50 MHz
MCLK; Master Clock Frequency; DVDD ≥ 1.26V 25
SCL SCL Clock Frequency 400 kHz
Audio input max ac signal swing
(IN1_L, IN1_R, IN2_L, IN2_R, IN3_L, IN3_R)		 CM = 0.75 V 0 0.530 0.75 or
AVDD-0.75(3) 		Vpeak
CM = 0.9 V 0 0.707 0.9 or
AVDD-0.9(3) 		Vpeak
LOL, LOR Stereo line output load resistance 0.6 10 kΩ
HPL, HPR Stereo headphone output load resistance Single-ended configuration 14.4 16 Ω
Headphone output load resistance Differential configuration 24.4 32 Ω
CLout Digital output load capacitance 10 pF
TOPR Operating Temperature Range –40 85 °C
(1) All grounds on board are tied together to prevent voltage differences of more than 0.2V maximum for any combination of ground signals.
(2) At DVDD values lower than 1.65V, the PLL does not function. Refer to the Maximum TLV320AIC3204 Clock Frequencies table in the TLV320AIC3204 Application Reference Guide(SLAA557) for details on maximum clock frequencies.
(3) Whichever is smaller.
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