Table 1. Multifunction Pin Assignments for Pins MCLK1, MCLK2, WCLK1, BCLK1, DIN1, DOUT1, WCLK2, BCLK2, DIN2, and DOUT2

Table 2. Multifunction Pin Assignments for Pins WCLK3, BCLK3, DIN3, DOUT3, GPIO1, GPIO2, GPO1, GPI1, GPI2, GPI3, and GPI4

10.3.2.2.1 Using the Headphone Amplifier

The headphone drivers are capable of driving a mixed combination of DAC signal, left and right ADC PGA signal, and LOL and LOR output signals by configuring B0_P1_R27-R29. The ADC PGA signals can be attenuated up to 36 dB before routing to headphone drivers by configuring B0_P1_R18 and B0_P1_R19. The line-output signals can be attenuated up to 78 dB before routing to headphone drivers by configuring B0_P1_R28 and B0_P1_R29. The level of the DAC signal can be controlled using the digital volume control of the DAC by configuring B0_P0_R64-R66. To control the output-voltage swing of headphone drivers, the headphone driver volume control provides a range of –6.0 dB to +14.0 dB⁽¹⁾ in steps of 1 dB. These can be configured by programming B0_P1_R27, B0_P1_R31, and B0_P1_R32. In addition, finer volume controls are also available when routing LOL or LOR to the headphone drivers by controlling B0_P1_R27-R28. These level controls are not meant to be used as dynamic volume control, but more to set output levels during initial device configuration. Register B0_P1_R9_D[6:5] allows the headphone output stage to be scaled to tradeoff power delivered vs quiescent power consumption. ⁽¹⁾

10.3.2.2.2 Ground-Centered Headphone Amplifier Configuration

Among the other advantages of the ground-centered connection is inherent freedom from turnon transients that can cause audible pops, sometimes at uncomfortable volumes.

10.3.2.2.2.1 Circuit Topology

The power supply hook up scheme for the ground centered configuration is shown in HVDD_18 terminal supplies the positive side of the headphone amplifier. CPVDD_18 terminal supplies the charge pump which in turn supplies the negative side of the headphone amplifier. Two capacitors are required for the charge pump circuit to work. These capacitors should be X7R rated.

Figure 22. Ground-Centered Headphone Connections

10.3.2.2.3 Stereo Unipolar Configuration

Figure 23. Unipolar Stereo Headphone Circuit

The left and right DAC channels are routed to the corresponding left and right headphone amplifier. This configuration is also used to drive line-level loads. To enable cap-coupled mode, B0_P1_R31_D7 should be set to 0. Note that the recommended range for the HVDD_18 supply in cap-coupled mode (1.65 V - 3.6 V) is different than the recommended range for the default ground-centered configuration (1.5 V - 1.95 V). In cap-coupled mode only, the Headphone output common mode can be controlled by changing B0_P1_R8_D[4:3].

10.3.2.2.3.2 Unipolar Turn-On Transient (Pop) Reduction

The TLV320AIC3212 headphone drivers also support pop-free operation in unipolar, ac-coupled configuration. Because the HPL and HPR are high-power drivers, pop can result due to sudden transient changes in the output drivers if care is not taken. The most critical care is required while using the drivers as stereo single-ended capacitively-coupled drivers as shown in Figure 23. The output drivers achieve pop-free power-up by using slow power-up modes. Conceptually, the circuit during power-up can be visualized as

Figure 24. Conceptual Circuit for Pop-Free Power-up

The value of R_pop can be chosen by setting register B0_P1_R11_D[1:0].

Table 8. R_pop Values (External C_c = 47uF)

B0_P1_R11_D[1:0]	Rpop VALUE
10	2 kΩ
01	6 kΩ
00	25 kΩ

To minimize audible artifacts, two parameters can be adjusted to match application requirements. The voltage V_load across R_load at the beginning of slow charging should not be more than a few mV. At that time the voltage across R_load can be determined as:

Equation 1.

For a typical R_load of 32 Ω, R_pop of 6 kΩ or 25 kΩ will deliver good results (see Table 8 for register settings).

According to the conceptual circuit in Figure 24, the voltage on PAD will exponentially settle to the output common-mode voltage based on the value of R_pop and C_c. Thus, the output drivers must be in slow power-up mode for time T, such that at the end of the slow power-on period, the voltage on V_pad is very close to the common-mode voltage. The TLV320AIC3212 allows the time T to be adjusted to allow for a wide range of R_load and C_c by programming B0_P1_R11_D[5:2]. For the time adjustments, the value of C_c is assumed to be 47μF. N=5 is expected to yield good results.

Table 9. N Values (External C_c = 47 µF)

B0_P1_R11_D[5:2]	Slow Charging Time = N * RC_Time_Constant (for Rpop and Cc = 47μF)
0000	N=0
0001	N=0.5
0010	N=0.625
0011	N=0.75
0100	N=0.875
0101	N=1.0
0110	N=2.0
0111	N=3.0
1000	N=4.0
1001	N=5.0 (Typical Value)
1010	N=6.0
1011	N=7.0
1100	N=8.0
1101	N=16 (Not valid for Rpop=25kΩ)
1110	N=24 (Not valid for Rpop=25kΩ)
1111	N=32 (Not valid for Rpop=25kΩ)

Again, for example, for R_load=32 Ω, C_c=47 μF and common mode of 0.9 V, the number of time constants required for pop-free operation is 5 or 6. A higher or lower C_c value will require higher or lower value for N.

During the slow-charging period, no signal is routed to the output driver. Therefore, choosing a larger than necessary value of N results in a delay from power-up to signal at output. At the same time, choosing N to be smaller than the optimal value results in poor pop performance at power-up.

The signals being routed to headphone drivers (for example, DAC and IN) often have DC offsets due to less-than-ideal processing. As a result, when these signals are routed to output drivers, the offset voltage causes a pop. To improve the pop-performance in such situations, a feature is provided to soft-step the DC-offset. At the beginning of the signal routing, a high-value attenuation can be applied which can be progressively reduced in steps until the desired gain in the channel is reached. The time interval between each of these gain changes can be controlled by programming B0_P1_R11_D[7:6]. This gain soft-stepping is applied only during the initial routing of the signal to the output driver and not during subsequent gain changes.

Table 10. Soft-Stepping Step Time

B0_P1_R11_D[7:6]	SOFT-STEPPING STEP TIME DURING INITIAL SIGNAL ROUTING
00	0 ms (soft-stepping disabled)
01	50ms
10	100ms
11	200ms

It is recommended to use the following sequence for achieving optimal pop performance at power-up:

1. Choose the value of R_pop, N (time constants) and soft-stepping step time for slow power-up.
2. Choose the configuration for output drivers, including common modes and output stage power connections
3. Select the signals to be routed to headphones.
4. Power-up the blocks driving signals into HPL and HPR, but keep it muted
5. Unmute HPL and HPR and set the desired gain setting.
6. Power-on the HPL and HPR drivers.
7. Unmute the block driving signals to HPL and HPR after the Driver PGA flags are set to indicate completion of soft-stepping after power-up. These flags can be read from B0_P1_R63_D[7:6].

It is important to configure the Headphone Output driver depop control registers before powering up the headphone; these register contents should not be changed when the headphone drivers are powered up.

Before powering down the HPL and HPR drivers, it is recommended that user read back the flags in B0_P1_R63. For example. before powering down the HPL driver, ensure that bit B0_P1_R63_D7 = 1 and bit B0_P1_R64_D7 = 1 if LOL is routed to HPL and bit B0_P1_R65_D5 = 1 if the Left Mixer is routed to HPL. The output driver should be powered down only after a steady-state power-up condition has been achieved. This steady state power-up condition also must be satisfied for changing the HPL/R driver mute control (setting both B0_P1_R31_D[5:0] and B0_P1_R32_D[5:0] to "11 1001"), that is, muting and unmuting should be done after the gain and volume controls associated with routing to HPL/R finished soft-stepping.

In the differential configuration of HPL and HPR, when no coupling capacitor is used, the slow charging method for pop-free performance need not be used. In the differential load configuration for HPL and HPR, it is recommended to not use the output driver MUTE feature, because a pop may result.

During the power-down state, the headphone outputs are weakly pulled to ground using an approximately 50kΩ resistor to ground, to maintain the output voltage on HPL and HPR terminals.

10.3.2.2.4 Mono Differential DAC to Mono Differential Headphone Output

Figure 25. Low Power Mono DAC to Differential Headphone

This configuration, available in unipolar configuration of the HP amplifier supplies, supports the routing of the two differential outputs of the mono, left channel DAC to the headphone amplifiers in differential mode (B0_P1_R27_D5 = 1 and B0_P1_R27_D2 = 1).

10.3.2.3.1 Line Out Amplifier Configurations

Signal mixing can be configured by programming B0_P1_R22 and B0_P1_R23. To route the output of Left DAC and Right DAC for stereo single-ended output, as shown in Figure 26, LDACM can be routed to LOL driver by setting B0_P1_R22_D7 = 1, and RDACM can be routed to LOR driver by setting B0_P1_R22_D6 = 1. Alternatively, stereo single-ended signals can also be routed through the mixer amplifiers by configuring B0_P1_R23_D[7:6]. For lowest-power operation, stereo single-ended signals can also be routed in direct terminal bypass with possible gains of 0dB, -6dB, or -12dB by configuring B0_P1_R23_D[4:3] and B0_P1_R23_D[1:0]. While each of these two bypass cases could be used in a stereo single-ended configuration, a mono differential input signal could also be used.

The output of the stereo line out drivers can also be routed to the stereo headphone drivers, with 0 dB to –72 dB gain controls in steps of 0.5 dB on each headphone channel. This enables the DAC output or bypass signals to be simultaneously played back to the stereo headphone drivers as well as stereo line-level drivers. This routing and volume control is achieved in B0_P1_R28 and B0_P1_R29.

Figure 26. Stereo Single-Ended Line-out

Additionally, the two line-level drivers can be configured to act as a mono differential line level driver by routing the output of LOL to LOR (B0_P1_R22_D2 = 1). This differential signal takes either LDACM, MAL, or IN1L-B as a single-ended mono signal and creates a differential mono output signal on LOL and LOR.

Figure 27. Single Channel Input to Differential Line-out

For digital outputs from the DAC, the two line-level drivers can be fed the differential output signal from the Right DAC by configuring B0_P1_R22_D5 = 1.

Figure 28. Mono DAC Output to Differential Line-out

10.3.3.1.1 ADC Processing Blocks

The TLV320AIC3212 offers a range of processing blocks which implement various signal processing capabilities along with decimation filtering. These processing blocks give users the choice of how much and what type of signal processing they may use and which decimation filter is applied.

The choice between these processing blocks is part of the PowerTune strategy to balance power conservation and signal-processing flexibility. Decreasing the use of signal-processing capabilities reduces the power consumed by the device. Table 11 gives an overview of the available processing blocks of the ADC channel and their properties. The Resource Class Column (RC) gives an approximate indication of power consumption.

The signal processing blocks available are:

• First-order IIR
• Scalable number of biquad filters
• Variable-tap FIR filter
• AGC

The processing blocks are tuned for common cases and can achieve high anti-alias filtering or low-group delay in combination with various signal processing effects such as audio effects and frequency shaping. The available first order IIR, BiQuad and FIR filters have fully user programmable coefficients.

10.3.4.1.1 DAC Processing Blocks

The TLV320AIC3212 implements signal processing capabilities and interpolation filtering via processing blocks. These fixed processing blocks give users the choice of how much and what type of signal processing they may use and which interpolation filter is applied.

The choice between these processing blocks is part of the PowerTune strategy balancing power conservation and signal processing flexibility. Less signal processing capability will result in less power consumed by the device. Table 12 gives an overview over all available processing blocks of the DAC channel and their properties. The Resource Class Column (RC) gives an approximate indication of power consumption.

The signal processing blocks available are:

• First-order IIR
• Scalable number of biquad filters
• 3D – Effect
• Beep Generator

The processing blocks are tuned for common cases and can achieve high image rejection or low group delay in combination with various signal processing effects such as audio effects and frequency shaping. The available first-order IIR and biquad filters have fully user-programmable coefficients.

10.3.8.1.1 I²C Control

The TLV320AIC3212 supports the I²C control protocol, and will respond by default (GPI3 and GPI4 grounded) to the 7-bit I²C address of 0011000. With the two I²C address terminals, GPI3 and GPI4, the device can be configured to respond to one of four 7-bit I²C addresses, 0011000, 0011001, 0011010, or 0011011. The full 8-bit I²C address can be calculated as:

8-Bit I²C Address = "00110" + GPI4 + GPI3 + R/W

Example: to write to the TLV320AIC3212 with GPI4 = 1 and GPI3 = 0 the 8-Bit I²C Address is "00110" + GPI4 + GPI3 + R/W = "00110100" = 0x34

I²C is a two-wire, open-drain interface supporting multiple devices and masters on a single bus. Devices on the I²C bus only drive the bus lines LOW by connecting them to ground; they never drive the bus lines HIGH. Instead, the bus wires are pulled HIGH by pullup resistors, so the bus wires are HIGH when no device is driving them LOW. This way, two devices cannot conflict; if two devices drive the bus simultaneously, there is no driver contention.

10.3.8.1.2 SPI Control

In the SPI control mode, the TLV320AIC3212 uses the terminals SCL as SS, GPI1 as SCLK, GPO1 as MISO, SDA as MOSI; a standard SPI port with clock polarity setting of 0 (typical microprocessor SPI control bit CPOL = 0) and clock phase setting of 1 (typical microprocessor SPI control bit CPHA = 1). The SPI port allows full-duplex, synchronous, serial communication between a host processor (the master) and peripheral devices (slaves). The SPI master (in this case, the host processor) generates the synchronizing clock (driven onto SCLK) and initiates transmissions. The SPI slave devices (such as the TLV320AIC3212) depend on a master to start and synchronize transmissions. A transmission begins when initiated by an SPI master. The byte from the SPI master begins shifting in on the slave MOSI terminal under the control of the master serial clock (driven onto SCLK). As the byte shifts in on the MOSI terminal, a byte shifts out on the MISO terminal to the master shift register.

The TLV320AIC3212 interface is designed so that with a clock-phase bit setting of 1 (typical microprocessor SPI control bit CPHA = 1), the master begins driving its MOSI terminal and the slave begins driving its MISO terminal on the first serial clock edge. The SSZ terminal can remain low between transmissions; however, the TLV320AIC3212 only interprets the first 8 bits transmitted after the falling edge of SSZ as a command byte, and the next 8 bits as a data byte only if writing to a register. Reserved register bits should be written to their default values. The TLV320AIC3212 is entirely controlled by registers. Reading and writing these registers is accomplished by an 8-bit command sent to the MOSI terminal of the part prior to the data for that register. The command is structured as shown in Figure 29. The first 7 bits specify the address of the register which is being written or read, from 0 to 127 (decimal). The command word ends with an R/W bit, which specifies the direction of data flow on the serial bus. In the case of a register write, the R/W bit should be set to 0. A second byte of data is sent to the MOSI terminal and contains the data to be written to the register. Reading of registers is accomplished in a similar fashion. The 8-bit command word sends the 7-bit register address, followed by the R/W bit = 1 to signify a register read is occurring. The 8-bit register data is then clocked out of the part on the MISO terminal during the second 8 SCLK clocks in the frame.

Figure 30. SPI Timing Diagram for Register Write

Figure 31. SPI Timing Diagram for Register Read