ZHCS851A March   2012  – September 2015 TLV320AIC3212

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用范围
  3. 3 描述
  4. 4 修订历史记录
  5. 5 说明 （续）
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  Electrical Characteristics, SAR ADC
    6. 8.6  Electrical Characteristics, ADC
    7. 8.7  Electrical Characteristics, Bypass Outputs
    8. 8.8  Electrical Characteristics, Microphone Interface
    9. 8.9  Electrical Characteristics, Audio DAC Outputs
    10. 8.10 Electrical Characteristics, Class-D Outputs
    11. 8.11 Electrical Characteristics, Miscellaneous
    12. 8.12 Electrical Characteristics, Logic Levels
    13. 8.13 Audio Data Serial Interface Timing (I2S): I2S/LJF/RJF Timing in Master Mode
    14. 8.14 Audio Data Serial Interface Timing (I2S): I2S/LJF/RJF Timing in Slave Mode
    15. 8.15 Typical DSP Timing: DSP/Mono PCM Timing in Master Mode
    16. 8.16 Typical DSP Timing: DSP/Mono PCM Timing in Slave Mode
    17. 8.17 I2C Interface Timing
    18. 8.18 SPI Timing
    19. 8.19 Typical Characteristics
      1. 8.19.1 Audio ADC Performance
      2. 8.19.2 Audio DAC Performance
      3. 8.19.3 Class-D Driver Performance
      4. 8.19.4 MICBIAS Performance
  9. 9 Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1 Device Connections
        1. 10.3.1.1 Digital Pins
        2. 10.3.1.2 Analog Pins
        3. 10.3.1.3 Multifunction Pins
      2. 10.3.2 Analog Audio I/O
        1. 10.3.2.1 Analog Low Power Bypass
        2. 10.3.2.2 Headphone Outputs
          1. 10.3.2.2.1 Using the Headphone Amplifier
          2. 10.3.2.2.2 Ground-Centered Headphone Amplifier Configuration
            1. 10.3.2.2.2.1 Circuit Topology
            2. 10.3.2.2.2.2 Charge Pump Setup and Operation
            3. 10.3.2.2.2.3 Output Power Optimization
            4. 10.3.2.2.2.4 Offset Correction and Start-Up
            5. 10.3.2.2.2.5 Ground-Centered Headphone Setup
              1. 10.3.2.2.2.5.1 High Audio Output Power, High Performance Setup
              2. 10.3.2.2.2.5.2 High Audio Output Power, Low Power Consumption Setup
              3. 10.3.2.2.2.5.3 Medium Audio Output Power, High Performance Setup
              4. 10.3.2.2.2.5.4 Lowest Power Consumption, Medium Audio Output Power Setup
          3. 10.3.2.2.3 Stereo Unipolar Configuration
            1. 10.3.2.2.3.1 Circuit Topology
            2. 10.3.2.2.3.2 Unipolar Turn-On Transient (Pop) Reduction
          4. 10.3.2.2.4 Mono Differential DAC to Mono Differential Headphone Output
        3. 10.3.2.3 Stereo Line Outputs
          1. 10.3.2.3.1 Line Out Amplifier Configurations
        4. 10.3.2.4 Differential Receiver Output
        5. 10.3.2.5 Stereo Class-D Speaker Outputs
      3. 10.3.3 ADC / Digital Microphone Interface
        1. 10.3.3.1 ADC Processing Blocks — Overview
          1. 10.3.3.1.1 ADC Processing Blocks
      4. 10.3.4 DAC
        1. 10.3.4.1 DAC Processing Blocks — Overview
          1. 10.3.4.1.1 DAC Processing Blocks
      5. 10.3.5 Device Power Consumption
      6. 10.3.6 Powertune
      7. 10.3.7 Clock Generation and PLL
      8. 10.3.8 Interfaces
        1. 10.3.8.1 Control Interfaces
          1. 10.3.8.1.1 I2C Control
          2. 10.3.8.1.2 SPI Control
        2. 10.3.8.2 Digital Audio Interfaces
      9. 10.3.9 Device Special Functions
    4. 10.4 Device Functional Modes
      1. 10.4.1 Recording Mode
      2. 10.4.2 Playback Mode
      3. 10.4.3 Analog Low Power Bypass Modes
    5. 10.5 Register Maps
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Application
      1. 11.2.1 Design Requirements
      2. 11.2.2 Detailed Design Procedure
        1. 11.2.2.1 Charge Pump Flying and Holding Capacitor
        2. 11.2.2.2 Reference Filtering Capacitor
        3. 11.2.2.3 MICBIAS
      3. 11.2.3 Application Curves
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Examples
  14. 14器件和文档支持
    1. 14.1 文档支持
      1. 14.1.1 相关文档　
    2. 14.2 社区资源
    3. 14.3 商标
    4. 14.4 静电放电警告
    5. 14.5 Glossary
  15. 15机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7 Pin Configuration and Functions

YZF Package
81-Pin DSBGA
Top View
TLV320AIC3212 s3262_RevB_WCSP_pinout_topview.gif

Pin Functions

PIN TYPE DESCRIPTION
NO. NAME
A1 AVDD3_33 P 3.3-V Power Supply for Micbias
A2 RECVSS P Receiver Driver Ground
A3 RECVDD_33 P 3.3-V Power Supply for Receiver Driver
A4 HPR O Right Headphone Output
A5 VNEG I/O Charge Pump Negative Supply
A6 CPFCM I/O Charge Pump Flying Capacitor M terminal
A7 CPVDD_18 P Power Supply Input for Charge Pump
A8 AVSS4 P Analog Ground for Class-D
A9 SPKLP O Left Channel P side Class-D Output
B1 MICDET I/O Headset Detection Pin
B2 RECP O Receiver Driver P side Output
B3 RECM O Receiver Driver M side Output
B4 HVDD_18 P Headphone Amp Power Supply
B5 HPL O Left Headphone Output
B6 CPVSS P Charge Pump Ground
B7 CPFCP I/O Charge Pump Flying Capacitor P Terminal
B8 SLVDD P Left Channel Class-D Output Stage Power Supply
B9 SLVSS P Left Channel Class-D Output Stage Ground
C1 IN4L I Analog Input 4 Left
C2 AVDD1_18 P 1.8-V Analog Power Supply
C3 MICBIAS_EXT O Output Bias Voltage for Headset Microphone.
C4 MICBIAS O Output Bias Voltage for Microphone to be used for on-board Microphones
C5 AVDD2_18 P 1.8-V Analog Power Supply
C6 LOL O Left Line Output
C7 AVDD4_18 P 1.8-V Analog Power Supply for Class-D
C8 SPKLM O Left Channel M side Class-D Output
C9 SPKRM O Right Channel M side Class-D Output
D1 VREF_AUDIO O Analog Reference Filter Output
D2 VREF_SAR I/O SAR ADC Voltage Reference Input or Internal SAR ADC Voltage Reference Bypass Capacitor Pin
D3 IN1L/AUX1 I Analog Input 1 Left, Auxiliary 1 Input to SAR ADC
(Special Function: Left Channel High Impedance Input for Capacitive Sensor Measurement)
D4 IN1R/AUX2 I Analog Input 1 Right, Auxiliary 2 Input to SAR ADC
(Special Function: Right Channel High Impedance Input for Capacitive Sensor Measurement)
D5 IN4R I Analog Input 4 Right
D6 HPVSS_SENSE I Headphone Ground Sense Terminal
D7 LOR O Right Line Output
D8 SRVSS P Right Channel Class-D Output Stage Ground
D9 SRVDD P Right Channel Class-D Output Stage Power Supply
E1 IN3R I Analog Input 3 Right
E2 IN3L I Analog Input 3 Left
E3 AVSS P Analog Ground
E4 AVSS1 P Analog Ground
E5 AVSS3 P Analog Ground
E6 AVSS2 P Analog Ground
E7 DVSS P Digital Ground
E8 SPK_V P Class-D Output Stage Power Supply (Connect to SRVDD through a Resistor)
E9 SPKRP O Right Channel P side Class-D Output
F1 IN2L I Analog Input 2 Left
F2 IN2R I Analog Input 2 Right
F3 AVDD_18 P 1.8-V Analog Power Supply
F4 DVSS P Digital Ground
F5 GPI3 I Multi Function Digital Input 3
Primary: (SPI_SELECT = 1)
ADC Bit Clock Input for Audio Serial Data Bus 1, 2, or 3 (Six-Wire Audio Interface)
ADC Word Clock Input for Audio Serial Data Bus 1, 2, or 3 (Six-Wire Audio Interface)
Secondary: (SPI_SELECT = 0)
I2C Address Bit 1 (I2C_ADDR0, LSB)
F6 GPI2 I Multi Function Digital Input 2
Primary:
General Purpose Input
Secondary:
Audio Serial Data Bus 1 Data Input
Digital Microphone Data Input
General Clock Input
Low-Frequency Clock Input
ADC Word Clock Input for Audio Serial Data Bus 1, 2, or 3 (Six-Wire Audio Interface)
ADC Bit Clock Input for Audio Serial Data Bus 1, 2, or 3 (Six-Wire Audio Interface)
F7 GPI4 I Multi Function Digital Input 4
Primary: (SPI_SELECT = 1)
ADC Bit Clock Input for Audio Serial Data Bus 1, 2, or 3 (Six-Wire Audio Interface)
ADC Word Clock Input for Audio Serial Data Bus 1, 2, or 3 (Six-Wire Audio Interface)
Secondary: (SPI_SELECT = 0)
I2C Address Bit 2 (I2C_ADDR1, MSB)
F8 IOVSS P Digital I/O Buffer Ground
F9 VBAT I Battery Monitor Voltage Input
G1 MCLK1 I Master Clock Input 1
G2 BCLK2 I/O Primary:
Audio Serial Data Bus 2 Bit Clock
Secondary:
General Purpose Input
General Purpose Output
General CLKOUT Output
ADC MOD Clock Output
SAR ADC Interrupt
INT1 Output
INT2 Output
General Clock Input
Low-Frequency Clock Input
G3 DIN2 I Primary:
Audio Serial Data Bus 2 Data Input
Secondary:
Digital Microphone Data Input
General Purpose Input
Low-Frequency Clock Input
G4 WCLK2 I/O Primary:
Audio Serial Data Bus 2 Word Clock
Secondary:
General Purpose Input
General Purpose Output
CLKOUT Output
ADC MOD Clock Output
SAR ADC Interrupt
INT1 Output
INT2 Output
Low-Frequency Clock Input
G5 WCLK3 I/O Primary:
Audio Serial Data Bus 3 Word Clock
Secondary:
General Purpose Output
General Purpose Input
Low-Frequency Clock Input
G6 DIN3 I Audio Serial Data Bus 3 Data Input
G7 SPI_SELECT I Control Interface Select
SPI_SELECT = 1: SPI Interface selected
SPI_SELECT = 0: I2C Interface selected
G8 RESET I Active Low Reset
G9 MCLK2 I Master Clock 2
Primary:
Clock Input
Secondary:
Digital Microphone Data Input
Low-Frequency Clock Input
H1 BCLK1 I/O Primary:
Audio Serial Data Bus 1 Bit Clock
Secondary:
General Clock Input
H2 DOUT1 O Primary:
Audio Serial Data Bus 1 Data Output
Secondary:
General Purpose Output
CLKOUT Output
SAR ADC Interrupt
INT1 Output
INT2 Output
H3 IOVDD P Digital I/O Buffer Supply
H4 SCL I/O I2C Interface Serial Clock (SPI_SELECT = 0)
SPI interface mode chip-select signal (SPI_SELECT = 1)
H5 SDA I/O I2C interface mode serial data input (SPI_SELECT = 0)
SPI interface mode serial data input (SPI_SELECT = 1)
H6 GPO1 O Multifunction Digital Output 1
Primary: (SPI_SELECT = 1)
Serial Data Output
Secondary: (SPI_SELECT = 0)
General Purpose Output
CLKOUT Output
ADC MOD Clock Output
SAR ADC Interrupt
INT1 Output
INT2 Output
H7 BCLK3 I/O Primary:
Audio Serial Data Bus 3 Bit Clock
Secondary:
General Purpose Input
General Purpose Output
Low-Frequency Clock Input
H8 GPIO2 I/O Multi Function Digital IO 2
Outputs:
General Purpose Output
ADC MOD Clock Output For Digital Microphone
CLKOUT Output
SAR ADC Interrupt
INT1 Output
INT2 Output
Audio Serial Data Bus 1 Bit Clock Output
ADC Word Clock Output for Audio Serial Data Bus 1, 2, or 3 (Six-Wire Audio Interface)
ADC Bit Clock Output for Audio Serial Data Bus 1, 2, or 3 (Six-Wire Audio Interface)
Inputs:
General Purpose Input
Digital Microphone Data Input
Audio Serial Data Bus 1 Bit Clock Input
General Clock Input
Low-Frequency Clock Input
ADC Word Clock Input for Audio Serial Data Bus 1, 2, or 3 (Six-Wire Audio Interface)
ADC Bit Clock Input for Audio Serial Data Bus 1, 2, or 3 (Six-Wire Audio Interface)
H9 IOVDD P Digital I/O Buffer Supply
J1 DIN1 I Primary:
Audio Serial Data Bus 1 Data Input
Secondary:
General Clock Input
Digital Microphone Data Input
J2 WCLK1 I/O Primary:
Audio Serial Data Bus 1 Word Clock
Secondary:
Low-Frequency Clock Input
General CLKOUT Output
J3 DVDD P 1.8V Digital Power Supply
J4 IOVSS P Digital I/O Buffer Ground
J5 GPI1 I Multifunction Digital Input 1
Primary: (SPI_SELECT = 1)
SPI Serial Clock
Secondary: (SPI_SELECT = 0)
Digital Microphone Data Input
General Clock Input
Low-Frequency Clock Input
General Purpose Input
ADC Word Clock Input for Audio Serial Data Bus 1, 2, or 3 (Six-Wire Audio Interface)
ADC Bit Clock Input for Audio Serial Data Bus 1, 2, or 3 (Six-Wire Audio Interface)
J6 DOUT2 O Primary:
Audio Serial Data Bus 2 Data Output
Secondary:
General Purpose Output
ADC MOD Clock Output
SAR ADC Interrupt
INT1 Output
INT2 Output
J7 DOUT3 O Primary:
Audio Serial Data Bus 3 Data Output
Secondary:
General Purpose Output
Audio Serial Data Bus 1 Word Clock Output
J8 GPIO1 I/O Multi Function Digital IO 1
Outputs:
General Purpose Output
ADC MOD Clock Output
CLKOUT Output
SAR ADC Interrupt
INT1 Output
INT2 Output
Audio Serial Data Bus 1 Word Clock Output
ADC Word Clock Output for Audio Serial Data Bus 1, 2, or 3 (Six-Wire Audio Interface)
ADC Bit Clock Output for Audio Serial Data Bus 1, 2, or 3 (Six-Wire Audio Interface)
Inputs:
General Purpose Input
Digital Microphone Data Input
Audio Serial Data Bus 1 Word Clock Input
General Clock Input
Low-Frequency Clock Input
ADC Word Clock Input for Audio Serial Data Bus 1, 2, or 3 (Six-Wire Audio Interface)
ADC Bit Clock Input for Audio Serial Data Bus 1, 2, or 3 (Six-Wire Audio Interface)
J9 DVDD P 1.8V Digital Power Supply
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