SLOS630C December   2010  – November 2014 TLV320AIC3256

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Block Diagram
  5. 5 Revision History
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  Handling Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  Electrical Characteristics, ADC
    6. 8.6  Electrical Characteristics, Bypass Outputs
    7. 8.7  Electrical Characteristics, Microphone Interface
    8. 8.8  Electrical Characteristics, Audio DAC Outputs
    9. 8.9  Electrical Characteristics, Misc.
    10. 8.10 Electrical Characteristics, Logic Levels
    11. 8.11 I2S/LJF/RJF Timing in Master Mode (see )
    12. 8.12 I2S/LJF/RJF Timing in Slave Mode (see )
    13. 8.13 DSP Timing in Master Mode (see )
    14. 8.14 DSP Timing in Slave Mode (see )
    15. 8.15 Digital Microphone PDM Timing (see )
    16. 8.16 I2C Interface Timing
    17. 8.17 SPI Interface Timing
    18. 8.18 Typical Characteristics
      1. 8.18.1 Typical Performance
      2. 8.18.2 FFT
  9. 9 Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1 Device Connections
        1. 10.3.1.1 Digital Pins
          1. 10.3.1.1.1 Multifunction Pins
        2. 10.3.1.2 Analog Pins
      2. 10.3.2 Analog Audio I/O
        1. 10.3.2.1 Analog Bypass
        2. 10.3.2.2 ADC Bypass Using Mixer Amplifiers
        3. 10.3.2.3 Headphone Output
        4. 10.3.2.4 Line Outputs
      3. 10.3.3 ADC
        1. 10.3.3.1 ADC Processing
          1. 10.3.3.1.1 ADC Processing Blocks
      4. 10.3.4 DAC
        1. 10.3.4.1 DAC Processing Blocks — Overview
      5. 10.3.5 PowerTune
      6. 10.3.6 Digital Audio IO Interface
      7. 10.3.7 Clock Generation and PLL
      8. 10.3.8 Control Interfaces
        1. 10.3.8.1 I2C Control
        2. 10.3.8.2 SPI Control
    4. 10.4 Device Functional Modes
      1. 10.4.1 MiniDSP
      2. 10.4.2 Software
    5. 10.5 Register Map
      1. 10.5.1 Register Map Summary
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Application
      1. 11.2.1 Design Requirements
        1. 11.2.1.1 Charge Pump Flying and Holding Capacitor
        2. 11.2.1.2 Reference Filtering Capacitor
        3. 11.2.1.3 MICBIAS
      2. 11.2.2 Detailed Design Procedures
        1. 11.2.2.1 Analog Input Connection
        2. 11.2.2.2 Analog Output Connection
      3. 11.2.3 Application Curves
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Example
  14. 14Device and Documentation Support
    1. 14.1 Documentation Support
      1. 14.1.1 Related Documentation
    2. 14.2 Trademarks
    3. 14.3 Electrostatic Discharge Caution
    4. 14.4 Glossary
  15. 15Mechanical, Packaging, and Orderable Information

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订购信息

5 Revision History

Changes from B Revision (January 2013) to C Revision

  • Added the Device information table, Handling Ratings table, Applications and Implementation section, Layout section, and the Device and Documentation Support sectionGo
  • Deleted "Acoustic Echo Cancellation (AEC)" and "Active Noise Cancellation (ANC)" from applications listGo
  • Added Note 1 to the Pin Functions tableGo
  • Added "Audio input mux ac signal swing" to the Recommended Operating Conditions table Go
  • Added the Digital Microphone PDM Timing (see ) sectionGo

Changes from A Revision (December 2010) to B Revision

  • Added WCSP package (YZF)Go
  • Updated block diagram to include Vsys pinGo
  • Updated diagram to include Vsys pinGo
  • Updated power supply section to include VsysGo

Changes from * Revision (December 2010) to A Revision

  • Changed "mV" to "mVRMS" for Input signal level units Go
  • Changed Gain Error value from 0.7 to 0.8Go
  • Changed Gain Error value from 0.5 to 0.8Go
  • Changed Noise, Idle Channel value from 6.9 to 6.7Go
  • Changed Bias voltage, Micbias Mode 0 value from 1.25 to 1.23Go
  • Changed Bias voltage, Micbias Mode 0 value from 1.25 to 1.23Go
  • Changed DAC Gain Error value from 0.4 to 0.5Go
  • Changed DAC Gain Error value from 0.1 to 0.5Go
  • Changed DAC channel separation condition from –1dB to –3dBGo
  • Changed 10µF to 1µF in Reference Noise conditions statementGo
  • Deleted min value from Decoupling Capacitor, changed typ value from 10 to 1µFGo
  • Moved value from typ to minGo
  • Moved value from typ to minGo
  • Changed WCLK delay min from 14 to 30nsGo
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