SLAS538B October   2007  – November 2016 TLV320AIC34

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Hardware Reset
      2. 9.3.2  I2C Bus Debug In A Glitched System
      3. 9.3.3  Digital Audio Data Serial Interface
      4. 9.3.4  TDM Data Transfer
      5. 9.3.5  Audio Data Converters
      6. 9.3.6  Audio Clock Generation
      7. 9.3.7  Stereo Audio ADC
        1. 9.3.7.1 Stereo Audio ADC High-pass Filter
      8. 9.3.8  Digital Audio Processing For Record Path
      9. 9.3.9  Automatic Gain Control (AGC)
      10. 9.3.10 Stereo Audio DAC
      11. 9.3.11 Digital Audio Processing For Playback
      12. 9.3.12 Digital Interpolation Filter
      13. 9.3.13 Delta-Sigma Audio DAC
      14. 9.3.14 Audio DAC Digital Volume Control
      15. 9.3.15 Increasing DAC Dynamic Range
      16. 9.3.16 Analog Output Common-Mode Adjustment
      17. 9.3.17 Audio DAC Power Control
      18. 9.3.18 Audio Analog Inputs
      19. 9.3.19 Analog Input Bypass Path Functionality
      20. 9.3.20 ADC PGA Signal Bypass Path Functionality
      21. 9.3.21 Input Impedance and VCM Control
      22. 9.3.22 Passive Analog Bypass During Power Down
      23. 9.3.23 MICBIAS_x Generation
      24. 9.3.24 Digital Microphone Connectivity
      25. 9.3.25 Analog Fully Differential Line Output Drivers
      26. 9.3.26 Analog High-Power Output Drivers
      27. 9.3.27 Short-Circuit Output Protection
      28. 9.3.28 Jack or Headset Detection
      29. 9.3.29 Output Stage Volume Controls
    4. 9.4 Device Functional Modes
      1. 9.4.1 I2C Control Mode
      2. 9.4.2 Right-Justified Mode
      3. 9.4.3 Left-Justified Mode
      4. 9.4.4 I2S Mode
      5. 9.4.5 DSP Mode
    5. 9.5 Programming
      1. 9.5.1 Digital Control Serial Interface
    6. 9.6 Register Maps
      1. 9.6.1 Register Description
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Related Links
    4. 13.4 Community Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • ZAS|87
散热焊盘机械数据 (封装 | 引脚)
订购信息

7 Pin Configuration and Functions

ZAS Package
87-Pin NFBGA
Top View
TLV320AIC34 pinout_slas538.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
ADDR_A L7 I I2C address control A
ADDR_B L8 I I2C address control B
AVDD_DAC B3 — Analog DAC voltage supply, 2.7 V – 3.6 V
AVSS_ADC D8 — Analog ADC ground supply, 0 V
AVSS_DAC D4, E4, F4, G4 — Analog DAC ground supply, 0 V
BCLK_A K3 I/O Audio serial data bus bit clock (input/output) A
BCLK_B L2 I/O Audio serial data bus bit clock (input/output) B
DIN_A K5 I Audio serial data bus data input (input) A
DIN_B L4 I Audio serial data bus data input (input) B
DOUT_A K6 O Audio serial data bus data output (output) A
DOUT_B L5 O Audio serial data bus data output (output) B
DRVDD B4, A4 — ADC analog and output driver voltage supply, 2.7 V to 3.6 V
DRVDD B9, A9 — Analog ADC and output driver voltage supply, 2.7 V to 3.6 V
DRVSS D5, D6, D7 — Analog output driver ground supply, 0 V
DVDD K1 — Digital core voltage supply, 1.65 V to 1.95 V
DVSS E8, F8, G8, H4, H5, H6, H8 — Digital core / I/O ground supply, 0 V
GPIO1_A J2 I/O General-purpose input/output #1–A
GPIO1_B J1 I/O General-purpose input/output #1–B
GPIO2_A H2 I/O General-purpose input/output #2 (input/output), digital microphone data input, PLL clock input, audio serial data bus bit clock input/output–A
GPIO2_B H1 I/O General-purpose input/output #2 (input/output), digital microphone data input, PLL clock input, audio serial data bus bit clock input/output–B
HPLCOM_A B7 O High-power output driver (left minus or multifunctional) A, capable of driving 8-Ω load
HPLCOM_B A7 O High-power output driver (left minus or multifunctional) B
HPLOUT_A B8 O High-power output driver (left plus) A, capable of driving 8-Ω load
HPLOUT_B A8 O High-power output driver (left plus) B
HPRCOM_A B6 O High-power output driver (right minus or multifunctional) A, capable of driving 8-Ω load
HPRCOM_B A6 O High-power output driver (right minus or multifunctional) B
HPROUT_A B5 O High-power output driver (right plus) A, capable of driving 8-Ω load
HPROUT_B A5 O High-power output driver (right plus) B
IOVDD H7, K7 — I/O voltage supply, 1.1 V to 3.6 V
LEFT_LOM_A D2 O Left line output (minus) A
LEFT_LOM_B D1 O Left line output (minus) B
LEFT_LOP_A C2 O Left line output (plus) A
LEFT_LOP_B C1 O Left line output (plus) B
LINE1LM_A L10 I MIC1 or Line1 analog input (left minus or multifunction) A
LINE1LM_B L11 I MIC1 or Line1 analog input (left minus or multifunction) B
LINE1LP_A K9 I MIC1 or Line1 analog input (left plus or multifunction) A
LINE1LP_B K8 I MIC1 or Line1 analog input (left plus or multifunction) B
LINE1RM_A J10 I MIC1 or Line1 analog input (right minus or multifunction) A
LINE1RM_B J11 I MIC1 or Line1 analog input (right minus or multifunction) B
LINE1RP_A K10 I MIC1 or Line1 analog input (right plus or multifunction) A
LINE1RP_B K11 I MIC1 or Line1 analog input (right plus or multifunction) B
LINE2LM_A G10 I MIC2 or Line2 analog input (left minus or multifunction) A
LINE2LM_B G11 I MIC2 or Line2 analog input (left minus or multifunction) B
LINE2LP_A H10 I MIC2 or Line2 analog input (left plus or multifunction) A
LINE2LP_B H11 I MIC2 or Line2 analog input (left plus or multifunction) B
LINE2RM_A E10 I MIC2 or Line2 analog input (right minus or multifunction) A
LINE2RM_B E11 I MIC2 or Line2 analog input (right minus or multifunction) B
LINE2RP_A F10 I MIC2 or Line2 analog input (right plus or multifunction) A
LINE2RP_B F11 I MIC2 or Line2 analog input (right plus or multifunction) B
MCLK_A K2 I Master clock input A
MCLK_B L1 I Master clock input B
MIC3L_A D10 I MIC3 input (left or multifunction) A
MIC3L_B D11 I MIC3 input (left or multifunction) B
MIC3R_A A10 I Microphone or line input 3 right A
MIC3R_B A11 I Microphone or line input 3 right B
MICBIAS_A B10 O Microphone bias voltage output A
MICBIAS_B B11 O Microphone bias voltage output B
MICDET_A C10 I Microphone detect A
MICDET_B C11 I Microphone detect B
MONO_LOM_A A2 O Mono line output (minus) A
MONO_LOM_B B1 O Mono line output (minus) B
MONO_LOP_A A3 O Mono line output (plus) A
MONO_LOP_B A1 O Mono line output (plus) B
RESET_A G2 I Reset A
RESET_B G1 I Reset B
RIGHT_LOM_A F2 O Right line output (minus) A
RIGHT_LOM_B F1 O Right line output (minus) B
RIGHT_LOP_A E2 O Right line output (plus) A
RIGHT_LOP_B E1 O Right line output (plus) B
SCL L9 I/O I2C serial clock
SDA L6 I/O I2C serial data input/output
WCLK_A K4 I/O Audio serial data bus word clock (input/output) A
WCLK_B L3 I/O Audio serial data bus word clock (input/output) B
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