米6体育平台手机版

ZHCS986B May 2012 – December 2018 TLV320DAC3203

PRODUCTION DATA.

封装选项

机械数据 (封装 | 引脚)

YZK|25
- MXBG031E
RGE|24
- MPQF124G

散热焊盘机械数据 (封装 | 引脚)

RGE|24
- QFND136Y

订购信息

7.3.1.1.1 Multifunction Pins

Table 1 shows the possible allocation of pins for specific functions. The PLL input, for example, can be programmed to be any of 4 pins (MCLK, BCLK, DIN, GPIO).

Table 1. Multifunction Pin Assignments

		1	2	3	4	5	6	7	8
	Pin Function	MCLK	BCLK	WCLK	DIN MFP1	DOUT MFP2	MFP3/ SCLK	MFP4/ MISO	GPIO MFP5
A	PLL Input	S⁽²⁾	S⁽³⁾		E				S⁽⁴⁾
B	Codec Clock Input	S⁽²⁾,D⁽⁵⁾	S⁽³⁾						S⁽⁴⁾
C	I²S BCLK input		S,D
D	I²S BCLK output		E⁽¹⁾
E	I²S WCLK input			E, D
F	I²S WCLK output			E
G	I²S ADC word clock input						E		E
H	I²S ADC WCLK out							E	E
I	I²S DIN				E, D
J	I²S DOUT					E, D
K	General Purpose Output I					E
K	General Purpose Output II							E
K	General Purpose Output III								E
L	General Purpose Input I				E
L	General Purpose Input II						E
L	General Purpose Input III								E
M	INT1 output					E		E	E
N	INT2 output					E		E	E
Q	Secondary I²S BCLK input						E		E
R	Secondary I²S WCLK in						E		E
S	Secondary I²S DIN						E		E
T	Secondary I²S DOUT							E
U	Secondary I²S BCLK OUT					E		E	E
V	Secondary I²S WCLK OUT					E		E	E
X	Aux Clock Output					E		E	E

(1) E: The pin is exclusively used for this function, no other function can be implemented with the same pin. (If GPIO/MFP5 has been allocated for General Purpose Output, it cannot be used as the INT1 output at the same time.)

(2) S⁽¹⁾: The MCLK pin can drive the PLL and Codec Clock inputs simultaneously.

(3) S⁽²⁾: The BCLK pin can drive the PLL and Codec Clock and audio interface bit clock inputs simultaneously.

(4) S⁽³⁾: The GPIO/MFP5 pin can drive the PLL and Codec Clock inputs simultaneously.

(5) D: Default Function