10.1 Layout Guidelines

For any high-speed comparator or amplifier, proper design and printed-circuit board (PCB) layout are necessary for optimal performance. Excess stray capacitance on the active input, or improper grounding, can limit the maximum performance of high-speed circuitry.

Minimizing resistance from the signal source to the comparator input is necessary to minimize the propagation delay of the complete circuit. The source resistance, along with input and stray capacitance, creates an RC filter that delays voltage transitions at the input, and reduces the amplitude of high-frequency signals. The input capacitance of the TLV350x, along with stray capacitance from an input pin to ground, results in several picofarads of capacitance.

The location and type of capacitors used for power-supply bypassing are critical to high-speed comparators. The suggested 2.2-μF tantalum capacitor does not need to be as close to the device as the 0.1-μF capacitor, and may be shared with other devices. The 2.2-μF capacitor buffers the power-supply line against ripple, and the 0.1-μF capacitor provides a charge for the comparator during high-frequency switching.

In a high-speed circuit, fast rising and falling switching transients create voltage differences across lines that would be at the same potential at DC. To reduce this effect, use a ground plane to reduce difference in voltage potential within the circuit board. A ground plane has the advantage of minimizing the effect of stray capacitances on the circuit board by providing a more desirable path for the current to flow. With a signal trace over a ground plane, at high-frequency the return current (in the ground plane) tends to flow right under the signal trace. Breaks in the ground plane (as simple as through-hole leads and vias) increase the inductance of the plane, making it less effective at higher frequencies. Breaks in the ground plane for necessary vias must be spaced randomly.

10.2 Layout Examples

Figure 22 shows an evaluation layout for the TLV3501 8-pin SOIC package; Figure 23 is for the 5-pin SOT-23 package. Both evaluation layouts are shown with SMA connectors that bring signals on and off the board. RT1 and RT2 are termination resistors for +V_IN and −V_IN, respectively. C1 and C2 are power-supply bypass capacitors. Place the 0.1-μF capacitor closest to the comparator. The ground plane is not shown, but the pads connecting the resistors and capacitors are shown. Figure 24 shows a schematic of this circuit.

Figure 22. TLV3501D (SOIC) Sample Layout

Figure 23. TLV3501DBV (SOT-23) Sample Layout

Figure 24. Layout Schematic