ZHCSQK0A October 2022 – December 2023 TLV3801-Q1 , TLV3802-Q1
PRODMIX
- 1
- 1 特性
- 2 应用
- 3 说明
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Detailed Description
- 8 Application and Implementation
- 9 Device and Documentation Support
- 10Mechanical, Packaging, and Orderable Information
8.2.3 Logic Clock Source to LVDS Transceiver
The Figure 8-5 shows a logic clock source being terminated and driven with the TLV380x-Q1 across a CAT6 Cable to receive an equivalent LVDS clock signal at the receiver end.
Figure 8-5 LVDS Clock Transceiver