米6体育平台手机版

ZHCSI23B April 2018 – March 2020 TLV62568A , TLV62569A

PRODUCTION DATA.

V_IN = 5.0 V, T_J = 25 °C, unless otherwise noted

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
SUPPLY
I_SD	Shutdown current into VIN pin	EN = 0 V		0.01	2	µA
V_UVLO	Under voltage lock out	V_IN falling		2.3	2.45	V
V_UVLO	under voltage lock out hysteresis			100		mV
T_JSD	Thermal shutdown	T_J rising		150		°C
T_JSD	Thermal shutdown	T_J falling		130		°C
LOGIC INTERFACE
V_IH	High-level input voltage at EN pin	2.5 ≤ V_IN ≤ 5.5	1.2			V
V_IL	Low-level input voltage at EN pin	2.5 ≤ V_IN ≤ 5.5			0.4	V
t_SS	Soft startup time	From EN high to 95% of VOUT nominal		0.9		ms
V_PG	Power good threshold	V_FB rising, referenced to V_FB nominal		95%
V_PG	Power good threshold	V_FB falling, referenced to V_FB nominal		90%
V_PG,OL	Low-level output voltage at PG pin	I_SINK = 1 mA			0.4	V
I_PG,LKG	Input leakage current into PG pin	V_PG = 5 V		100		nA
t_PG,DLY	Power good delay time	V_FB falling		40		µs
OUTPUT
V_FB	Feedback regulation voltage		0.588	0.6	0.612	V
I_FB	Input leakage current into FB pin	V_FB = 0.6 V		10		nA
R_DS(on)	High-side FET on resistance			100		mΩ
R_DS(on)	Low-side FET on resistance			60		mΩ
I_LIM	High-side FET current limit	TLV62569A, TLV62569AP	3			A
I_LIM	High-side FET current limit	TLV62568A, TLV62568AP	2			A
f_SW	Switching frequency			1.5		MHz