ZHCSHH2B January 2018 – October 2018 TLV6710
PRODUCTION DATA.
PARAMETER | DESIGN REQUIREMENT | DESIGN RESULT |
---|---|---|
Monitored voltage | 24-V nominal, rising (VMON(OV)) and falling (VMON(UV)) threshold
±10% nominal (26.4 V and 21.6 V, respectively) |
VMON(OV) = 26.4 V ±2.7%, VMON(UV) = 21.6 V ±2.7% |
Output logic voltage | 3.3-V CMOS | 3.3-V CMOS |
Maximum current consumption | 30 µA | 24 µA |