8.3.2 Output Pin (OUT)

In a typical TLV6713 application, the output is connected to a GPIO input of the processor (such as a digital signal processor [DSP], central processing unit [CPU], field-programmable gate array [FPGA], or application-specific integrated circuit [ASIC]).

The TLV6713 provides an open-drain output (OUT) rated to 25 V, independant of supply voltage, and can sink up to 40 mA.. A pullup resistor is required to hold the line high when the output goes to a high-impedance state. Connect this pullup resistor to a voltage rail that meets the logic requirements of the downstream device. To ensure the proper voltage level, give some consideration when choosing the pullup resistor value. The pullup resistor value is determined by V_OL, output capacitive loading, and the open-drain leakage current (I_D(leak)). These values are specified in the Electrical Characteristicstable.

Table 2 and Input Pin (SENSE) describe how the output is asserted or high impedance. See Figure 1 for a timing diagram that describes the relationship between threshold voltage and the respective output.