ZHCSI89D November   2017  – September 2024 TLV755P

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Undervoltage Lockout (UVLO)
      2. 6.3.2 Enable (EN)
      3. 6.3.3 Internal Foldback Current Limit
      4. 6.3.4 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Normal Operation
      2. 6.4.2 Dropout Operation
      3. 6.4.3 Disabled
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Input and Output Capacitor Selection
      2. 7.1.2 Dropout Voltage
      3. 7.1.3 Exiting Dropout
      4. 7.1.4 Reverse Current
      5. 7.1.5 Power Dissipation (PD)
        1. 7.1.5.1 Estimating Junction Temperature
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Input Current
        2. 7.2.2.2 Thermal Dissipation
      3. 7.2.3 Application Curve
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Examples
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Device Nomenclature
    2. 8.2 接收文档更新通知
    3. 8.3 支持资源
    4. 8.4 Trademarks
    5. 8.5 静电放电警告
    6. 8.6 术语表
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • DYD|5
  • DBV|5
  • DQN|4
  • DRV|6
散热焊盘机械数据 (封装 | 引脚)
订购信息

5.4 Thermal Information

PCB THERMAL METRIC(1) (2) TLV755 UNIT
DYD (SOT-23-5) DQN (X2SON) DBV (SOT-23-5) DRV (WSON)
5 PINS 4 PINS 5 PINS 6 PINS
EVM RθJA Junction-to-ambient thermal resistance 60.3 N/A 100.8 N/A °C/W
ψJT Junction-to-top characterization parameter 14.2 N/A 23.3 N/A
ψJB Junction-to-board characterization parameter 35.9 N/A 67.8 N/A
JEDEC RθJA Junction-to-ambient thermal resistance 92.5 168.4 231.1 100.2 °C/W
RθJC(top)
Junction-to-case (top) thermal resistance

 119.8 139.1 118.4 108.5
RθJB
Junction-to-board thermal resistance

 45.8 101.4 64.4 64.3
ψJT Junction-to-top characterization parameter 16.7 5.6 28.4 10.4
ψJB Junction-to-board characterization parameter 44.9 101.7 63.8 64.8
RθJC(bot) Junction-to-case (bottom) thermal resistance 34.3 88.4 N/A 34.7
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application note.
(2) JEDEC thermal metrics apply to JEDEC standard PCB (2s2p, no vias to internal plane and bottom layer). EVM metrics  apply to the LP087A EVM with an exposed pad SOT-23-5 (DYD) layout. 
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