ZHCSJX8J August 2018 – May 2021 TLV803E , TLV809E , TLV810E
PRODMIX
RESET remains logic low (deasserted) as long as VDD is above the positive threshold (VIT+). If VDD falls below the negative threshold (VIT–), then reset is asserted and RESET transistions to logic high (VOH).
When VDD rises above VIT+, the delay circuit holds RESET active and logic high for the specified reset delay period (tD). When the reset delay has elapsed the RESET pin transistions to low voltage (VOL).