ZHCSMJ5F june 2010 – december 2020 TLV809
PRODUCTION DATA
9.1.2 Reset During Power-Up and Power-Down
The device output is valid when VDD is greater than 1.1 V. When VDD is less than 1.1 V, the output transistor turns off and becomes high impedance. The voltage on the RESET pin rises to the voltage level connected to the pullup resistor. Figure 9-2 shows a typical waveform for power-up.
Figure 9-2 Power-Up Response