The primary constraint for this application is choosing the correct device to monitor the supply voltage of the microprocessor. The TLV840-Q1 can monitor any voltage between 0.8 V and 5.4 V. Depending on how far away from the nominal voltage rail the user wants the voltage supervisor to trigger determines the correct voltage supervisor variant to choose. In this example, the first TLV840-Q1 triggers when the 3.3-V rail falls to 2.9 V. The second TLV840-Q1 triggers a reset when the 1.2-V rail falls to 0.9 V. The secondary constraint for this application is the reset time delay that must be at least 25 ms to allow the microprocessor, and all other devices using the 3.3-V rail, enough time to startup correctly before the 1.2-V rail is enabled via the LDO. Because a minimum time is required, the user must account for capacitor tolerance. For applications with ambient temperatures ranging from –40°C to +125°C, C_CT can be calculated using R_CT and solving for C_CT in Equation 2. Solving Equation 2 for 25 ms gives a minimum capacitor value of 0.0403 µF which is rounded up to a standard value 0.047 µF to account for capacitor tolerance.

A 1 µF decoupling capacitor is connected to the VDD pin as a good analog design practice. The pull-up resistor is only required for the Open-Drain device variants and is calculated to ensure that V_OL does not exceed max limit given the Isink possible at the expected supply voltage. In this design example nominal VDD is 1.2 V but dropping to 0.9 V. In Section 7.5, max V_OL provides 15 µA I sink for 0.7 V VDD, which is the closest voltage to this design example. Using 15 µA of Isink and 300 mV max V_OL, gives us 40 kΩ for the pull-up resistor. Any value higher than 40 kΩ would ensure that V_OL will not exceed 300 mV max specification.