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SNVSBY3A November 2020 – April 2021 TLV840-Q1

PRODUCTION DATA

封装选项

机械数据 (封装 | 引脚)

DBV|5
- MPDS018T

散热焊盘机械数据 (封装 | 引脚)

订购信息

7.7 Timing Diagrams

_{(1) t_{D (no cap)} is included in t_STRT time delay. If
t_D delay is programmed by an external capacitor connected to
CT pin then t_D programmed time will be
added to the startup time, VDD slew rate =
100 mV / μs.}

_{(2) Open-Drain timing diagram
where RESET is pulled up to VDD via an external pull-up
resistor}

_{(3)
RESET output is undefined when V_DD is
< V_POR}

Figure 7-1 Timing Diagram TLV840MADL-Q1 (Open-Drain Active-Low)

_{(4) t_{D (no cap)} is
included in t_STRT time delay. If t_D delay is
programmed by an external capacitor connected to CT pin then t_D
programmed time will be
added to the startup
time, VDD slew rate = 100 mV / μs.}

_{(5)
RESET output is undefined when V_DD is
< V_POR and limited to V_OL for V_DD slew
rate = 100 mV / μS}

Figure 7-2 Timing Diagram TLV840MAPL-Q1 (Push-Pull Active-Low)

_{(6) t_{D (no cap)} is
included in t_STRT time delay. If t_D delay is
programmed by an external capacitor connected to CT pin then t_D
programmed time will be
added to the startup
time, VDD slew rate = 100 mV / μs.}

Figure 7-3 Timing Diagram TLV840MAPH-Q1 (Push-Pull Active-High)