The manual reset (MR) input allows a processor GPIO or other logic circuits to initiate a reset. A logic low on MR with pulse duration longer than t_{MR_PW} will cause the reset output to assert. After MR returns to a logic high
(V_{MR_H}) and VDD is above V_IT+, reset is deasserted after the user programmed reset time delay (t_D) expires.

The minimum duration for which MR is held under V_{MR_L} must be at least 1% of t_{MR_tD}. Otherwise, the effective reset delay will be shorter roughly by the difference between 1% of t_{MR_tD} and the actual MR pulse width. For large capacitor based delays this difference could be noticeable unless care is taken to lengthen the MR pulse width.

MR is internally connected to VDD through a pull-up resistor R_MR shown in Section 8.2. If the logic signal controlling MR is less than VDD, then additional current flows from VDD into MR internally. For minimum current consumption, drive MR to either VDD or GND. V_MR should not be higher than VDD voltage.

Figure 8-4 Timing Diagram MR and RESET