ZHCSRX5B April   2023  – August 2024 TLV9361-Q1 , TLV9362-Q1 , TLV9364-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information for Single Channel
    5. 5.5 Thermal Information for Dual Channel
    6. 5.6 Thermal Information for Quad Channel
    7. 5.7 Electrical Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 EMI Rejection
      2. 6.3.2 Thermal Protection
      3. 6.3.3 Capacitive Load and Stability
      4. 6.3.4 Electrical Overstress
      5. 6.3.5 Overload Recovery
      6. 6.3.6 Typical Specifications and Distributions
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Low-Side Current Measurement
      2. 7.2.2 Design Requirements
      3. 7.2.3 Detailed Design Procedure
      4. 7.2.4 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 TINA-TI (Free Software Download)
        2. 8.1.1.2 TI Precision Designs
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 接收文档更新通知
    4. 8.4 支持资源
    5. 8.5 Trademarks
    6. 8.6 静电放电警告
    7. 8.7 术语表
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

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5.7 Electrical Characteristics

For VS = (V+) – (V–) = 4.5 V to 40 V (±2.25 V to ±20 V) at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VOS Input offset voltage VCM = V– ±0.4 ±1.7 mV
TA = –40°C to 125°C ±2
dVOS/dT Input offset voltage drift VCM = V– TA = –40°C to 125°C ±1.25 µV/℃
PSRR Input offset voltage versus power supply VCM = V–, VS = 5 V to 40 V(1) TA = –40°C to 125°C ±1.5 ±7.5 μV/V
DC channel separation 1 µV/V
INPUT BIAS CURRENT
IB Input bias current ±10 pA
IOS Input offset current ±10 pA
NOISE
EN Input voltage noise f = 0.1 Hz to 10 Hz   6 μVPP
  1   µVRMS
eN Input voltage noise density f = 1 kHz 8.5   nV/√Hz
f = 10 kHz   6  
iN Input current noise density f = 1 kHz   100   fA/√Hz
INPUT VOLTAGE RANGE
VCM Common-mode voltage range (V–) (V+) – 2 V
CMRR Common-mode rejection ratio VS = 40 V, V– < VCM < (V+) – 2 V TA = –40°C to 125°C 95 110 dB
VS = 5 V, V– < VCM < (V+) – 2 V(1) 75 85
INPUT IMPEDANCE
ZID Differential 100 || 9 MΩ || pF
ZICM Common-mode 6 || 1 TΩ || pF
OPEN-LOOP GAIN
AOL Open-loop voltage gain VS = 40 V, VCM = VS / 2,
(V–) + 0.1 V < VO < (V+) –  0.1 V		 115 130 dB
VS = 40 V, VCM = VS / 2,
(V–) + 0.12 V < VO < (V+) –  0.12 V		 TA = –40°C to 125°C 130
VS = 5 V, VCM = VS / 2,
(V–) + 0.1 V < VO < (V+) –  0.1 V(1)		 100 120
TA = –40°C to 125°C 120
FREQUENCY RESPONSE
GBW Gain-bandwidth product 10.6 MHz
SR Slew rate VS = 40 V, G = +1, VSTEP = 10 V, CL = 20 pF(3) 25 V/μs
tS Settling time To 0.1%, VS = 40 V, VSTEP = 10 V, G = +1, CL = 20 pF 0.65 μs
To 0.1%, VS = 40 V, VSTEP = 2 V, G = +1, CL = 20 pF 0.3
To 0.01%, VS = 40 V, VSTEP = 10 V, G = +1, CL = 20 pF 0.86
To 0.01%, VS = 40 V, VSTEP = 2 V, G = +1, CL = 20 pF 0.44
Phase margin G = +1, RL = 10 kΩ, CL = 20 pF 64 °
Overload recovery time VIN  × gain > VS 170 ns
THD+N Total harmonic distortion + noise VS = 40 V, VO = 3 VRMS, G = 1, f = 1 kHz, RL = 10 kΩ 0.0001%
120 dB
VS = 10 V, VO = 3 VRMS, G = 1, f = 1 kHz, RL = 128 Ω 0.0056%
85 dB
VS = 10 V, VO = 0.4 VRMS, G = 1, f = 1 kHz, RL = 32 Ω 0.00056%
105 dB
OUTPUT
  Voltage output swing from rail Positive and negative
rail headroom		 VS = 40 V, RL = no load   10 mV
VS = 40 V, RL = 10 kΩ   60 100
VS = 40 V, RL = 2 kΩ   250 400
ISC Short-circuit current ±60(2) mA
CLOAD Capacitive Load Drive See Figure 5-28 pF
ZO Open-loop output impedance IO = 0 A See Figure 5-25 Ω
POWER SUPPLY
IQ Quiescent current per amplifier IO = 0 A 2.6 3 mA
TA = –40°C to 125°C 3.2
(1) Specified by characterization only.
(2) At high supply voltage, placing the TLV936x in a sudden short to mid-supply or ground will lead to rapid thermal shutdown.  Output current greater than ISC can be achieved if rapid thermal shutdown is avoided as per Figure 5-12.
(3) See Figure 5-11 for more information.
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