Figure 7-13 and Figure 7-10 show examples of standard I²C three byte read command supported by the TMAG5173-Q1. The starting byte contains 7-bit secondary device address and the R/W command bit '0'. The MSB of the second byte contains the conversion trigger command bit. Writing '1' at this trigger bit will start a new conversion after the register address decoding is completed. The 7 LSB bits of the second byte contains the starting register address for the write command. After receiving ACK signal from secondary, the primary send the secondary address once again with R/W command bit as '1'. The secondary starts to send the corresponding register data. It will send successive register data with each successive ACK from primary. If CRC is enabled, the secondary will send the fifth CRC byte based off the CRC calculation of immediate past 4 register bytes.

Figure 7-9 Standard 3-Byte I²C Read With CRC Disabled, CRC_EN = 0b

Figure 7-10 Standard 3-Byte I²C Read With CRC Enabled, CRC_EN = 1b