11.1 Layout Guidelines

For the TMDS181 on a high-K board: It is required to solder the PowerPAD™ onto the thermal land to ground. A thermal land is the area of solder-tinned-copper underneath the PowerPAD package. On a high-K board, the TMDS181 can operate over the full temperature range by soldering the PowerPAD onto the thermal land.

On a low-K board: For the device to operate across the temperature range on a low-K board, the designer must use a 1-oz Cu trace connecting the GND pins to the thermal land. A simulation shows R_θJA = 100.84°C/W allowing 545 mW power dissipation at 70°C ambient temperature. A general PCB design guide for PowerPAD packages is provided in PowerPAD Thermally Enhanced Package, SLMA002. TI recommends using at a minimum a four-layer stack to accomplish a low-EMI PCB design. TI recommends six layers as the TMDS181 is a two-voltage-rail device.

• Routing the high-speed TMDS traces on the top layer avoids the use of vias (and their discontinuities) and allows for clean interconnects from the HDMI connectors to the retimer inputs and outputs. It is important to match the electrical length of these high-speed traces to minimize both inter-pair and intra-pair skew.
• Placing a solid ground plane next to the high-speed single layer establishes controlled impedance for transmission link interconnects and provides an excellent low-inductance path for the return current flow.
• Placing a power plane next to the ground plane creates an additional high-frequency bypass capacitance.
• Routing slower-speed control signals on the bottom layer allows for greater flexibility because these signal links usually have margin to tolerate discontinuities such as vias.
• If an additional supply voltage plane or signal layer is needed, add a second power/ground plane system to the stack to keep symmetry. This makes the stack mechanically stable and prevents it from warping. Also, the power and ground plane of each power system can be placed closer together, thus increasing the high-frequency bypass capacitance significantly.

Figure 38. Recommended 4- or 6-Layer PCB Stack

11.2 Layout Example

A. If ARC is not used, tie a 500 kΩ resistor to GND at the SPDIF_IN pin.

B. The 55 Ω resistor to GND on the ARC_OUT pin is implementation specific and may not be needed if it is already implemented elsewhere.

Figure 39. Layout Example – Source Side