Table 1. Temperature Data Format

7.3.2.1 Bus Overview

The device that initiates the transfer is called a master, and the devices controlled by the master are slaves. The bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions.

To address a specific device, a START condition is initiated, indicated by pulling the data line (SDA) from a HIGH to LOW logic level while SCL is HIGH. All slaves on the bus shift in the slave address byte, with the last bit indicating whether a read or write operation is intended. During the ninth clock pulse, the slave being addressed responds to the master by generating an Acknowledge and pulling SDA LOW.

Data transfer is then initiated and sent over eight clock pulses followed by an Acknowledge Bit. During data transfer, SDA must remain stable while SCL is HIGH because any change in SDA while SCL is HIGH is interpreted as a control signal.

When all data are transferred, the master generates a STOP condition indicated by pulling SDA from LOW to HIGH, while SCL is HIGH.

7.3.2.2 Serial Bus Address

To program the TMP100 and TMP101 devices, the master must first address slave devices through a slave address byte. The slave address byte consists of seven address bits and a direction bit indicating the intent of executing a read or write operation.

The TMP100 device features two address pins to allow up to eight devices to be addressed on a single I²C interface. Table 2 describes the pin logic levels used to properly connect up to eight devices. Float indicates the pin is left unconnected. The state of pins ADD0 and ADD1 is sampled on the first I²C bus communication and must be set before any activity on the interface.

The TMP101 device features one address pin and an ALERT pin, allowing up to three devices to be connected per bus. Pin logic levels are described in Table 3. The address pins of the TMP100 and TMP101 devices are read after reset or in response to an I²C address acquire request. Following reading, the state of the address pins is latched to minimize power dissipation associated with detection.

7.3.2.3 Writing and Reading to the TMP100 and TMP101

Accessing a particular register on the TMP100 and TMP101 devices is accomplished by writing the appropriate value to the Pointer Register. The value for the Pointer Register is the first byte transferred after the I²C slave address byte with the R/W bit LOW. Every write operation to the TMP100 and TMP101 devices requires a value for the Pointer Register (see Figure 7).

When reading from the TMP100 and TMP101 devices, the last value stored in the Pointer Register by a write operation is used to determine which register is read by a read operation. To change the register pointer for a read operation, a new value must be written to the Pointer Register. This action is accomplished by issuing an I²C slave address byte with the R/W bit LOW, followed by the Pointer Register Byte. No additional data are required. The master can then generate a START condition and send the I²C slave address byte with the R/W bit HIGH to initiate the read command; see Figure 8 for details of this sequence. If repeated reads from the same register are desired, the Pointer Register bytes do not have to be continually sent because the TMP100 and TMP101 devices remember the Pointer Register value until that value is changed by the next write operation.

7.3.2.4 Slave Mode Operations

The TMP100 and TMP101 devices can operate as a slave receiver or slave transmitter.

7.3.2.5 SMBus Alert Function

The TMP101 device supports the SMBus Alert function. When the TMP101 device is operating in Interrupt Mode (TM = 1), the ALERT pin of the TMP101 device can be connected as an SMBus Alert signal. When a master senses that an ALERT condition is present on the ALERT line, the master sends an SMBus Alert command (00011001) on the bus. If the ALERT pin of the TMP101 device is active, the TMP101 device acknowledges the SMBus Alert command and responds by returning its slave address on the SDA line. The eighth bit (LSB) of the slave address byte indicates if the temperature exceeding T_HIGH or falling below T_LOW caused the ALERT condition. For POL = 0, this bit is LOW if the temperature is greater than or equal to THIGH. This bit is HIGH if the temperature is less than TLOW. The polarity of this bit is inverted if POL = 1; see Figure 9 for details of this sequence.

If multiple devices on the bus respond to the SMBus Alert command, arbitration during the slave address portion of the SMBus alert command determine which device clears its ALERT status. If the TMP101 device wins the arbitration, its ALERT pin becomes inactive at the completion of the SMBus Alert command. If the TMP101 loses the arbitration, its ALERT pin remains active.

The TMP100 device also responds to the SMBus ALERT command if its TM bit is set to 1. Because the device does not have an ALERT pin, the device must periodically poll the device by issuing an SMBus Alert command. If the TMP100 device generates an ALERT, the device acknowledges the SMBus Alert command and returns its slave address in the next byte.

7.3.2.6 General Call

The TMP100 and TMP101 devices respond to the I²C General Call address (0000000) if the eighth bit is 0. The device acknowledges the General Call address and responds to commands in the second byte. If the second byte is 00000100, the TMP100 and TMP101 devices latch the status of their address pins, but do not reset. If the second byte is 00000110, the TMP100 and TMP101 devices latch the status of their address pins and reset their internal registers.

7.3.2.7 High-Speed Mode

In order for the I²C bus to operate at frequencies above 400 kHz, the master device must issue an Hs-mode master code (00001XXX) as the first byte after a START condition to switch the bus to high-speed operation. The TMP100 and TMP101 devices do not acknowledge this byte as required by the I²C specification, but do switch their input filters on SDA and SCL and their output filters on SDA to operate in Hs-mode, allowing transfers at up to 2 MHz. After the Hs-mode master code is issued, the master transmits an I²C slave address to initiate a data transfer operation. The bus continues to operate in Hs-mode until a STOP condition occurs on the bus. Upon receiving the STOP condition, the TMP100 and TMP101 devices switch the input and output filter back to fast-mode operation.

7.3.2.8 POR (Power-On Reset)

The TMP100 and TMP101 devices both have on-chip, power-on reset circuits that reset the device to default settings when the device is powered on. This circuit activates when the power supply is less than 0.3 V for more than 100 ms. If the TMP100 and TMP101 devices are powered down by removing supply voltage from the device, but the supply voltage is not assured to be less than 0.3 V, TI recommends issuing a General Call reset command on the I²C interface bus to ensure that the TMP100 and TMP101 devices are completely reset.

7.4.3.1 Comparator Mode (TM = 0)

In Comparator Mode (TM = 0), the ALERT pin is activated when the temperature equals or exceeds the value in the T_HIGH register and remains active until the temperature falls below the value in the T_LOW register. For more information on the Comparator Mode, see the High- and Low-Limit Registers section.

7.4.3.2 Interrupt Mode (TM = 1)

In Interrupt Mode (TM = 1), the ALERT pin is activated when the temperature exceeds T_HIGH or goes below the T_LOW registers. The ALERT pin is cleared when the host controller reads the temperature register. For more information on the interrupt mode, see the High- and Low-Limit Registers section.

7.5.1.1 Pointer Register Byte (pointer = N/A) [reset = 00h]

7.5.1.2 Pointer Addresses of the TMP100 and TMP101 Registers

Table 6. Byte 1 of the Temperature Register

Table 7. Byte 2 of the Temperature Register

Table 8. Configuration Register Format

7.5.3.1 Shutdown Mode (SD)

The Shutdown Mode of the TMP100 and TMP101 devices allows the user to save maximum power by shutting down all device circuitry other than the serial interface, which reduces current consumption to less than 1 µA. For the TMP100 and TMP101 devices, Shutdown Mode is enabled when the SD bit is 1. The device shuts down when the current conversion is completed. For SD equal to 0, the device maintains continuous conversion.

7.5.3.2 Thermostat Mode (TM)

The Thermostat Mode bit of the TMP101 device indicates to the device whether to operate in Comparator Mode (TM = 0) or Interrupt Mode (TM = 1). For more information on comparator and interrupt modes, see High- and Low-Limit Registers.

7.5.3.3 Polarity (POL)

The Polarity bit of the TMP101 device lets the user adjust the polarity of the ALERT pin output. If the POL bit is set to 0 (default), the ALERT pin becomes active low. When the POL bit is set to 1, the ALERT pin becomes active high and the state of the ALERT pin is inverted. The operation of the ALERT pin in various modes is illustrated in Figure 11.

Figure 11. Output Transfer Function Diagrams

7.5.3.4 Fault Queue (F1, F0)

A fault condition occurs when the measured temperature exceeds the user-defined limits set in the T_HIGH and T_LOW Registers. Additionally, the number of fault conditions required to generate an alert can be programmed using the Fault Queue. The Fault Queue is provided to prevent a false alert resulting from environmental noise. The Fault Queue requires consecutive fault measurements in order to trigger the alert function. If the temperature falls below T_LOW before reaching the number of programmed consecutive faults limit, the count is reset to 0. Table 9 defines the number of measured faults that can be programmed to trigger an alert condition in the device.

7.5.3.5 Converter Resolution (R1, R0)

The Converter Resolution bits control the resolution of the internal analog-to-digital converter (ADC), thus allowing the user to maximize efficiency by programming for higher resolution or faster conversion time. Table 10 identifies the Resolution bits and the relationship between resolution and conversion time.

7.5.3.6 OS/ALERT (OS)

The TMP100 and TMP101 devices feature a One-Shot Temperature Measurement Mode. When the device is in Shutdown Mode, writing 1 to the OS/ALERT bit starts a single temperature conversion. The device returns to the shutdown state at the completion of the single conversion. This feature is useful to reduce power consumption in the TMP100 and TMP101 when continuous temperature monitoring is not required.

Reading the OS/ALERT bit provides information about the Comparator Mode status. The state of the POL bit inverts the polarity of data returned from the OS/ALERT bit. For POL = 0, the OS/ALERT reads as 1 until the temperature equals or exceeds T_HIGH for the programmed number of consecutive faults, causing the OS/ALERT bit to read as 0. The OS/ALERT bit continues to read as 0 until the temperature falls below T_LOW for the programmed number of consecutive faults when the OS/ALERT bit again reads as 1. The status of the TM bit does not affect the status of the OS/ALERT bit.

Table 11. Byte 1 of the T_HIGH Register

Table 12. Byte 2 of the T_HIGH Register

Table 13. Byte 1 of the T_LOW Register

Table 14. Byte 2 of the T_LOW Register