ZHCSIX4I August 2007 – June 2024 TMP102
PRODUCTION DATA
The first byte transmitted by the controller is the target address, with the R/W bit low. The TMP102 then acknowledges reception of a valid address. The next byte transmitted by the controller is the pointer register. The TMP102 then acknowledges reception of the pointer register byte. The next byte or bytes are written to the register addressed by the pointer register. The TMP102 acknowledges reception of each data byte. The controller can terminate data transfer by generating a START or STOP condition..