SBOS545D February   2011  – December 2018 TMP103

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Application Diagram
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 One-Shot Mode
      3. 7.4.3 Continuous Conversion Mode
    5. 7.5 Programming
      1. 7.5.1  Temperature Watchdog Function
      2. 7.5.2  Conversion Rate
      3. 7.5.3  Shutdown Mode (M1 = 0, M0 = 0)
      4. 7.5.4  One-Shot (M1 = 0, M0 = 1)
      5. 7.5.5  Continuous Conversion Mode (M1 = 1)
      6. 7.5.6  Bus Overview
      7. 7.5.7  Serial Interface
      8. 7.5.8  Serial Bus Address
      9. 7.5.9  Writing and Reading Operation
      10. 7.5.10 Slave Mode Operations
        1. 7.5.10.1 Slave Receiver Mode
        2. 7.5.10.2 Slave Transmitter Mode
      11. 7.5.11 General Call
      12. 7.5.12 High-Speed (Hs) Mode
      13. 7.5.13 Timeout Function
      14. 7.5.14 Multiple Device Access
        1. 7.5.14.1 Multiple Device Access Write
        2. 7.5.14.2 Multiple Device Access Read
      15. 7.5.15 NOISE
    6. 7.6 Register Maps
      1. 7.6.1 Pointer Register
      2. 7.6.2 Temperature Register
      3. 7.6.3 Configuration Register
      4. 7.6.4 Temperature Limit Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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机械数据 (封装 | 引脚)
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6.6 Timing Requirements

See (1)
FAST MODE HIGH-SPEED MODE UNIT
MIN MAX MIN MAX
f(SCL) SCL operating frequency, VS > 1.7 V 0.001 0.4 0.001 3.4 MHz
f(SCL) SCL operating frequency, VS < 1.7 V 0.001 0.4 0.001 2.75 MHz
t(BUF) Bus free time between STOP and START condition 600 160 ns
t(HDSTA) Hold time after repeated START condition.
After this period, the first clock is generated.		 100 100 ns
t(SUSTA) Repeated START condition setup time 100 100 ns
t(SUSTO) STOP condition setup Time 100 100 ns
t(HDDAT) Data hold time 20 400 10 125 ns
t(SUDAT) Data setup time 100 10 ns
t(LOW) SCL clock low period, VS > 1.7 V 1300 160 ns
t(LOW) SCL clock low period, VS < 1.7 V 1300 200 ns
t(HIGH) SCL clock high period 600 60 ns
tF Clock/data fall time 300 ns
tR Clock/data rise time 300 160 ns
tR Clock/data rise time for SCLK ≤ 100 kHz 1000 ns
(1) Values based on a statistical analysis of a one-time sample of devices. Minimum and maximum values are not guaranteed and not production tested.

The TMP103 is two-wire and SMBus compatible. Figure 1 to Figure 5 describe the various operations on the TMP103. Parameters for Figure 1 are defined in Timing Requirements. Bus definitions are:

Bus Idle: Both SDA and SCL lines remain high.

Start Data Transfer: A change in the state of the SDA line, from high to low, while the SCL line is high, defines a START condition. Each data transfer is initiated with a START condition.

Stop Data Transfer: A change in the state of the SDA line from low to high while the SCL line is high defines a STOP condition. Each data transfer is terminated with a repeated START or STOP condition.

Data Transfer: The number of data bytes transferred between a START and a STOP condition is not limited and is determined by the master device.

Acknowledge: Each receiving device, when addressed, is obliged to generate an Acknowledge bit. A device that acknowledges must pull down the SDA line during the Acknowledge clock pulse in such a way that the SDA line is stable low during the high period of the Acknowledge clock pulse. Setup and hold times must be taken into account. On a master receive, the termination of the data transfer can be signaled by the master generating a Not-Acknowledge (1) on the last byte transmitted by the slave.

TMP103 ai_two_wire_tim_bos397.gif
NOTE: P = STOP, S = START.
Figure 1. Two-Wire Timing Diagram
TMP103 ai_two_wire_write_bos545.gif
1. The value of A0, A1, and A2 are determined by the TMP103 version; see Table 2.
Figure 2. Two-Wire Timing Diagram for Write Word Format
TMP103 ai_two_wire_read_bos545.gif
1. The value of A0, A1, and A2 are determined by the TMP103 version; see Table 2.
Figure 3. Two-Wire Timing Diagram for Read Word Format
TMP103 ai_two_wire_mda_write_bos545.gif
1. All TMP103 devices on the bus acknowledge the byte.
Figure 4. Two-Wire Timing Diagram MDA Write Word Format
TMP103 ai_two_wire_mda_read_bos545.gif
1. All TMP103 devices on the bus acknowledge the byte.
2. The master must issue an acknowledge for each byte read to read all of the TMP103 devices on the bus.
3. Three TMP103 devices used in this case; up to eight devices can be used (see Table 2).
Figure 5. Two-Wire Timing Diagram MDA Read Word Format Using Figure 16 (Typical Application)
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