11.1 Layout Guidelines

Mount the TMP107-Q1 to a PCB as shown in Figure 44. Obtaining acceptable performance with alternate layout schemes is possible, however this layout produces good results and is intended as a guideline.

• Bypass the V+ pin to ground with a low-ESR ceramic bypass-capacitor. The typical recommended bypass capacitance is a 0.1-μF ceramic capacitor with a X5R or X7R dielectric. The optimum placement is closest to the V+ and GND pins of the device. Take care to minimize the loop area formed by the bypass-capacitor connection, the V+ pin, and the GND pin of the IC.
• Use larger copper area pads to reduce self-heating and lower thermal resistance to the environment.
• If possible, use PCB boards with thick copper layers.
• If possible, do not use stain to protect the IC because stain can increase thermal resistance.

11.2 Layout Example

Figure 44. Layout Example