ZHCSHX1E March   2018  – August 2021 TMP1075

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 说明（续）
  6. 6 Device Comparison
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  Electrical Characteristics:TMP1075
    6. 8.6  Electrical Characteristics: TMP1075N
    7. 8.7  Timing Requirements:TMP1075
    8. 8.8  Timing Requirements: TMP1075N
    9. 8.9  Switching Characteristics
    10. 8.10 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Digital Temperature Output
      2. 9.3.2 I2C and SMBus Serial Interface
        1. 9.3.2.1  Bus Overview
        2. 9.3.2.2  Serial Bus Address
        3. 9.3.2.3  Pointer Register
          1. 9.3.2.3.1 Pointer Register Byte [reset = 00h]
        4. 9.3.2.4  Writing and Reading to the TMP1075
        5. 9.3.2.5  Operation Mode
          1. 9.3.2.5.1 Receiver Mode
          2. 9.3.2.5.2 Transmitter Mode
        6. 9.3.2.6  SMBus Alert Function
        7. 9.3.2.7  General Call- Reset Function
        8. 9.3.2.8  High-Speed Mode (HS)
        9. 9.3.2.9  Coexists in I3C Mixed Fast Mode
        10. 9.3.2.10 Time-Out Function
      3. 9.3.3 Timing Diagrams
      4. 9.3.4 Two-Wire Timing Diagrams
    4. 9.4 Device Functional Modes
      1. 9.4.1 Shutdown Mode (SD)
      2. 9.4.2 One-Shot Mode (OS)
      3. 9.4.3 Continuous Conversion Mode (CC)
      4. 9.4.4 Thermostat Mode (TM)
        1. 9.4.4.1 Comparator Mode (TM = 0)
        2. 9.4.4.2 Interrupt Mode (TM = 1)
        3. 9.4.4.3 Polarity Mode (POL)
    5. 9.5 Register Map
      1. 9.5.1 Register Descriptions
        1. 9.5.1.1 Temperature Register (address = 00h) [default reset = 0000h]
        2. 9.5.1.2 Configuration Register (address = 01h) [default reset = 00FFh (60A0h TMP1075N)]
        3. 9.5.1.3 Low Limit Register (address = 02h) [default reset = 4B00h]
        4. 9.5.1.4 High Limit Register (address = 03h) [default reset = 5000h]
        5. 9.5.1.5 Device ID Register (address = 0Fh) [default reset = 7500]
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Migrating From the xx75 Device Family
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 接收文档更新通知
    2. 13.2 支持资源
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 术语表
  14. 14Mechanical, Packaging, and Orderable Information

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9.3.2.5.2 Transmitter Mode

The first byte is transmitted by the host and is the device address, with the R/W bit high. The target device acknowledges reception of a valid device address. The next byte is transmitted by the device and is the most significant byte of the register indicated by the Pointer register. The host acknowledges reception of the data byte. The next byte transmitted by the device is the least significant byte. The host acknowledges reception of the data byte. The host can terminate data transfer by generating a Not-Acknowledge on reception of any data byte, or generating a START or STOP condition.
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