7.3.1 Digital Temperature Output

The temperature register of the TMP275-Q1 is a 12-bit, read-only register that stores the output of the most recent conversion. Two bytes must be read to obtain data, and are described in Table 5 and Table 6. Note that byte 1 is the most significant byte and is followed by byte 2, the least significant byte. The first 12 bits are used to indicate temperature, with all remaining bits equal to zero. The least significant byte does not have to be read if that information is not needed. The data format for temperature is summarized in Table 1. Following power-up or reset, the Temperature register reads 0°C until the first conversion is complete. The user can obtain 9, 10, 11, or 12 bits of resolution by addressing the Configuration register and setting the resolution bits accordingly. For 9-, 10-, or 11-bit resolution, the most significant bits (MSBs) in the Temperature register are used with the unused least significant bits (LSBs) set to zero.

7.3.2 Serial Interface

The TMP275-Q1 operates only as a slave device on the SMBus, two-wire, and I²C interface-compatible bus. Connections to the bus are made through the open-drain I/O lines SDA and SCL. The SDA and SCL pins feature integrated spike-suppression filters and Schmitt triggers to minimize the effects of input spikes and bus noise. The TMP275-Q1 supports the transmission protocol for fast (up to 400 kHz) and high-speed (up to 2.38 MHz) modes. All data bytes are transmitted most significant bit (MSB) first.

7.3.3 Bus Overview

The device that initiates the transfer is called a master, and the devices controlled by the master are slaves. The bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions.

To address a specific device a START condition is initiated, indicated by pulling the data line (SDA) from a high to a low logic level when SCL is high. All slaves on the bus shift in the slave address byte, with the last bit indicating whether a read or write operation is intended. During the ninth clock pulse, the slave being addressed responds to the master by generating an Acknowledge bit and pulling SDA low.

Data transfer is then initiated and sent over eight clock pulses followed by an Acknowledge bit. During data transfer, SDA must remain stable when SCL is high because any change in SDA when SCL is high is interpreted as a control signal.

When all data are transferred, the master generates a STOP condition indicated by pulling SDA from low to high when SCL is high.

7.3.4 Serial Bus Address

To communicate with the TMP275-Q1, the master must first address slave devices through a slave address byte. The slave address byte consists of seven address bits and a direction bit indicating the intent of executing a read or write operation.

The TMP275-Q1 features three address pins, allowing up to eight devices to be connected per bus. Pin logic levels are described in Table 2. The address pins of the TMP275-Q1 are read after reset, at the start of communication, or in response to a two-wire address acquire request. Following reading the state of the pins, the address is latched to minimize power dissipation associated with detection.

7.3.5 Timing Diagrams

The TMP275-Q1 is two-wire, SMBus, and I²C interface compatible. Figure 7 to Figure 10 describe the various operations on the TMP275-Q1. The following list provides bus definitions. Parameters for Figure 7 are defined in the Timing Requirements table.

Bus Idle: Both the SDA and SCL lines remain high.

Start Data Transfer: A change in the state of the SDA line, from high to low when the SCL line is high defines a START condition. Each data transfer is initiated with a START condition.

Stop Data Transfer: A change in the state of the SDA line from low to high when the SCL line is high defines a STOP condition. Each data transfer is terminated with a repeated START or STOP condition.

Data Transfer: The number of data bytes transferred between a START and a STOP condition is not limited and is determined by the master device. The receiver acknowledges the transfer of data.

Acknowledge: Each receiving device, when addressed, is obliged to generate an Acknowledge bit. A device that acknowledges must pull down the SDA line during the Acknowledge clock pulse in such a way that the SDA line is stable low during the high period of the Acknowledge clock pulse. Setup and hold times must be taken into account. On a master receive, the termination of the data transfer can be signaled by the master generating a Not-Acknowledge bit on the last byte that is transmitted by the slave.

7.3.5.1 Two-Wire Timing Diagrams

Figure 7. Two-Wire Timing Diagram

Figure 8. Two-Wire Timing Diagram for TMP275-Q1 Write Word Format

NOTE:

Address pins A0, A1, and A2 = 0.

Figure 9. Two-Wire Timing Diagram for Read Word Format

NOTE:

Address pins A0, A1, and A2 = 0.

Figure 10. Timing Diagram for SMBus ALERT

7.4.1 Shutdown Mode (SD)

The shutdown mode of the TMP275-Q1 allows the user to save maximum power by shutting down all device circuitry other than the serial interface, thus reducing current consumption to typically less than 0.1 μA. Shutdown mode is enabled when the SD bit is 1; the device shuts down when the current conversion is completed. When SD is equal to 0, the device maintains a continuous conversion state.

7.4.2 Thermostat Mode (TM)

The thermostat mode bit of the TMP275-Q1 indicates to the device whether to operate in comparator mode (TM = 0) or interrupt mode (TM = 1). For more information on comparator and interrupt modes, see the High- and Low-Limit Registers section.

7.4.3 One-Shot (OS)

The TMP275-Q1 features a one-shot temperature measurement mode. When the device is in shutdown mode, writing a 1 to the OS bit starts a single temperature conversion. The device returns to the shutdown state at the completion of the single conversion. This feature is useful for reducing power consumption in the TMP275-Q1 when continuous temperature monitoring is not required. When the configuration register is read, OS always reads zero.

7.5.1 Pointer Register

Figure 11 shows the internal register structure of the TMP275-Q1. The 8-bit Pointer register of the device is used to address a given data register. The Pointer register uses the two LSBs to identify which of the data registers must respond to a read or write command. Table 3 identifies the bits of the Pointer register byte. Table 4 describes the pointer address of the registers available in the TMP275-Q1. The power-up reset value of P1/P0 is 00.

Figure 11. Internal Register Structure of the TMP275-Q1

7.5.2 Temperature Register

The Temperature register of the TMP275-Q1 is a 12-bit, read-only register that stores the output of the most recent conversion. Two bytes must be read to obtain data and are described in Table 5 and Table 6. Note that byte 1 is the most significant byte and is followed by byte 2, the least significant byte. The first 12 bits are used to indicate temperature, with all remaining bits equal to zero. The least significant byte does not have to be read if that information is not needed. The data format for temperature is summarized in Table 1. Following power-up or reset, the Temperature register reads 0°C until the first conversion is complete.

7.5.3 Configuration Register

The Configuration register is an 8-bit read/write register used to store bits that control the operational modes of the temperature sensor. Read and write operations are performed MSB first. The format of the Configuration register for the TMP275-Q1 is shown in Table 7, followed by a breakdown of the register bits. The power-up or reset value of the Configuration register is all bits equal to 0.

7.5.4 Polarity (POL)

The Polarity bit of the TMP275-Q1 allows the user to adjust the polarity of the ALERT pin output. If POL = 0, the ALERT pin is active low, as shown in Figure 12. For POL = 1, the ALERT pin is active high and the state of the ALERT pin is inverted.

Figure 12. Output Transfer Function Diagrams

7.5.5 Fault Queue (F1/F0)

A fault condition is defined as when the measured temperature exceeds the user-defined limits set in the T_HIGH and T_LOW registers. Additionally, the number of fault conditions required to generate an alert can be programmed using the fault queue. The fault queue is provided to prevent a false alert resulting from environmental noise. The fault queue requires consecutive fault measurements to trigger the Alert function. Table 8 defines the number of measured faults that can be programmed to trigger an Alert condition in the device. For the T_HIGH and T_LOW register format and byte order, see the High- and Low-Limit Registers section.

7.5.6 Converter Resolution (R1/R0)

The converter resolution bits control the resolution of the internal analog-to-digital converter (ADC). This control allows the user to maximize efficiency by programming for higher resolution or faster conversion time. Table 9 identifies the resolution bits and the relationship between resolution and conversion time.

7.5.7 High- and Low-Limit Registers

In comparator mode (TM = 0), the ALERT pin of the TMP275-Q1 becomes active when the temperature equals or exceeds the value in T_HIGH and generates a consecutive number of faults according to fault bits F1 and F0. The ALERT pin remains active until the temperature falls below the indicated T_LOW value for the same number of faults.

In interrupt mode (TM = 1), the ALERT pin becomes active when the temperature equals or exceeds T_HIGH for a consecutive number of fault conditions. The ALERT pin remains active until a read operation of any register occurs, or the device successfully responds to the SMBus alert response address. The ALERT pin is also cleared if the device is placed in shutdown mode. When cleared, the ALERT pin only becomes active again by the temperature falling below T_LOW. When the temperature falls below T_LOW, the ALERT pin becomes active and remains active until cleared by a read operation of any register or a successful response to the SMBus alert response address. When the ALERT pin is cleared, the above cycle repeats, with the ALERT pin becoming active when the temperature equals or exceeds T_HIGH. The ALERT pin can also be cleared by resetting the device with the General-Call Reset command. This action also clears the state of the internal registers in the device, returning the device to comparator mode (TM = 0).

Both operational modes are represented in Figure 12. Table 10, Table 11, Table 12, and Table 13 describe the format for the T_HIGH and T_LOW registers. Note that the most significant byte is sent first, followed by the least significant byte. Power-up reset values for T_HIGH and _TLOW are:

T_HIGH = 80°C and T_LOW = 75°C

The format of the data for T_HIGH and T_LOW is the same as for the Temperature register.

All 12 bits for the Temperature, T_HIGH, and, T_LOW registers are used in the comparisons for the Alert function for all converter resolutions. The three LSBs in T_HIGH and T_LOW can affect the Alert output even if the converter is configured for 9-bit resolution.