米6体育平台手机版

ZHCSKD0I September 2009 – October 2019 TMP431 , TMP432

PRODUCTION DATA.

封装选项

机械数据 (封装 | 引脚)

DGK|8
- MPDS028E

散热焊盘机械数据 (封装 | 引脚)

订购信息

6.6 Timing Requirements⁽¹⁾

			FAST MODE		HIGH-SPEED MODE		UNIT
			MIN	MAX	MIN	MAX	UNIT
f_(SCL)	SCL operating frequency	V+	0.001	0.4	0.001	2.5	MHz
t_(BUF)	Bus free time between STOP and START condition		600		160		ns
t_(HDSTA)	Hold time after repeated START condition. After this period, the first clock is generated.		100		100		ns
t_(SUSTA)	Repeated START condition setup time		100		100		ns
t_(SUSTO)	STOP condition setup time		100		100		ns
t_(HDDAT)	Data hold time		0⁽²⁾	900	0⁽³⁾	80	ns
t_(SUDAT)	Data setup time		100		25		ns
t_(LOW)	SCL clock LOW period	V+	1300		265		ns
t_(HIGH)	SCL clock HIGH period		600		60		ns
t_FD	Data fall time			300		160	ns
t_RC	Clock rise time			300		40	ns
t_RC	Clock rise time	SCLK ≤ 100 kHz		1000			ns
t_FC	Clock fall time			300		40	ns

(1) Values based on a statistical analysis of a one-time sample of devices. Minimum and maximum values are not specified and not production tested.

(2) For cases with a fall time of SCL less than 20 ns or where the rise time or fall time of SDA is less than 20 ns, the hold time must be greater than 20 ns.

(3) For cases with a fall time of SCL less than 10 ns or where the rise or fall time of SDA is less than 10 ns, the hold time must be greater than 10 ns.

封装选项

机械数据 (封装 | 引脚)

散热焊盘机械数据 (封装 | 引脚)

订购信息

6.6 Timing Requirements(1)

6.6 Timing Requirements⁽¹⁾