8.5.3 Timing Diagrams

The TMP43x are Two-Wire and SMBus-compatible. Figure 13 to Figure 17 describe the various operations on the TMP43x. Parameters for Figure 13 are defined in Figure 14. Bus definitions are given below:

Bus Idle: Both SDA and SCL lines remain high.

Start Data Transfer: A change in the state of the SDA line from high to low when the SCL line is high defines a START condition. Each data transfer is initiated with a START condition.

Stop Data Transfer: A change in the state of the SDA line from low to high when the SCL line is high defines a STOP condition. Each data transfer terminates with a STOP or a repeated START condition.

Data Transfer: The number of data bytes transferred between a START and a STOP condition is not limited and is determined by the master device. The receiver acknowledges the transfer of data.

Acknowledge: Each receiving device, when addressed, is obliged to generate an Acknowledge bit. A device that acknowledges must pull down the SDA line during the Acknowledge clock pulse in such a way that the SDA line is stable low during the high period of the Acknowledge clock pulse. Setup and hold times must be taken into account. On a master receive, data transfer termination can be signaled by the master generating a Not-Acknowledge on the last byte that has been transmitted by the slave.

Figure 13. Two-Wire Timing Diagram

1. Slave address 1001100 (TMP431A, 32A, and 31C) shown. Slave address changes for TMP431B, 32B, and 31D. See 机械、封装和可订购信息 for more details.

Figure 14. Two-Wire Timing Diagram for Write Word Format

1. Slave address 1001100 (TMP431A, 32A, and 31C) shown. Slave address changes for TMP431B, 32B, and 31D. See 机械、封装和可订购信息 for more details.

2. Master must leave SDA high to terminate a single-byte read operation.

Figure 15. Two-Wire Timing Diagram for Single-Byte Read Format

1. Slave address 1001100 (TMP431A, 32A, and 31C) shown. Slave address changes for TMP431B, 32B, and 31D. See 机械、封装和可订购信息 for more details.

2. Master must leave SDA high to terminate a two-byte read operation.

Figure 16. Two-Wire Timing Diagram for Two-Byte Read Format

1. Slave address 1001100 (TMP431A, 32A, and 31C) shown. Slave address changes for TMP431B, 32B, and 31D. See 机械、封装和可订购信息 for more details.

Figure 17. Timing Diagram for SMBus ALERT