ZHCSA18F March   2009  – February 2021 TMS320C28341 , TMS320C28342 , TMS320C28343 , TMS320C28343-Q1 , TMS320C28344 , TMS320C28345 , TMS320C28346 , TMS320C28346-Q1

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1. 3.1 Functional Block Diagram
  4. 4 Revision History
  5. 5 Device Comparison
    1. 5.1 Related Products
  6. 6 Terminal Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Signal Descriptions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings (1) (1)
    2. 7.2 ESD Ratings – Automotive
    3. 7.3 ESD Ratings – Commercial
    4. 7.4 Recommended Operating Conditions
    5. 7.5 Power Consumption Summary
      1. 7.5.1 TMS320C28346/C28344 (1) Current Consumption by Power-Supply Pins at 300-MHz SYSCLKOUT
      2. 7.5.2 TMS320C28345/C28343 (1) Current Consumption by Power-Supply Pins at 200-MHz SYSCLKOUT
      3. 7.5.3 Reducing Current Consumption
    6. 7.6 Electrical Characteristics
    7. 7.7 Thermal Resistance Characteristics
      1. 7.7.1 ZHH Package
      2. 7.7.2 ZFE Package
    8. 7.8 Thermal Design Considerations
    9. 7.9 Timing and Switching Characteristics
      1. 7.9.1 Timing Parameter Symbology
        1. 7.9.1.1 General Notes on Timing Parameters
        2. 7.9.1.2 Test Load Circuit
        3. 7.9.1.3 Device Clock Table
          1. 7.9.1.3.1 Clocking and Nomenclature (300-MHz Devices)
          2. 7.9.1.3.2 Clocking and Nomenclature (200-MHz Devices)
      2. 7.9.2 Power Sequencing
        1. 7.9.2.1 Power Management and Supervisory Circuit Solutions
        2. 7.9.2.2 Reset ( XRS) Timing Requirements
      3. 7.9.3 Clock Requirements and Characteristics
        1. 7.9.3.1 XCLKIN/X1 Timing Requirements – PLL Enabled
        2. 7.9.3.2 XCLKIN/X1 Timing Requirements – PLL Disabled
        3. 7.9.3.3 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled) (1) (1)
        4. 7.9.3.4 Timing Diagram
      4. 7.9.4 Peripherals
        1. 7.9.4.1 General-Purpose Input/Output (GPIO)
          1. 7.9.4.1.1 GPIO - Output Timing
            1. 7.9.4.1.1.1 General-Purpose Output Switching Characteristics
          2. 7.9.4.1.2 GPIO - Input Timing
            1. 7.9.4.1.2.1 General-Purpose Input Timing Requirements
          3. 7.9.4.1.3 Sampling Window Width for Input Signals
          4. 7.9.4.1.4 Low-Power Mode Wakeup Timing
            1. 7.9.4.1.4.1 IDLE Mode Timing Requirements (1)
            2. 7.9.4.1.4.2 IDLE Mode Switching Characteristics (1)
            3. 7.9.4.1.4.3 IDLE Mode Timing Diagram
            4. 7.9.4.1.4.4 STANDBY Mode Timing Requirements
            5. 7.9.4.1.4.5 STANDBY Mode Switching Characteristics
            6. 7.9.4.1.4.6 STANDBY Mode Timing Diagram
            7. 7.9.4.1.4.7 HALT Mode Timing Requirements
            8. 7.9.4.1.4.8 HALT Mode Switching Characteristics
            9. 7.9.4.1.4.9 HALT Mode Timing Diagram
        2. 7.9.4.2 Enhanced Control Peripherals
          1. 7.9.4.2.1 Enhanced Pulse Width Modulator (ePWM) Timing
            1. 7.9.4.2.1.1 ePWM Timing Requirements (1)
            2. 7.9.4.2.1.2 ePWM Switching Characteristics
          2. 7.9.4.2.2 Trip-Zone Input Timing
            1. 7.9.4.2.2.1 Trip-Zone Input Timing Requirements (1)
          3. 7.9.4.2.3 High-Resolution PWM Timing
            1. 7.9.4.2.3.1 High-Resolution PWM Characteristics at SYSCLKOUT = (150–300 MHz)
          4. 7.9.4.2.4 Enhanced Capture (eCAP) Timing
            1. 7.9.4.2.4.1 Enhanced Capture (eCAP) Timing Requirements (1)
            2. 7.9.4.2.4.2 eCAP Switching Characteristics
          5. 7.9.4.2.5 Enhanced Quadrature Encoder Pulse (eQEP) Timing
            1. 7.9.4.2.5.1 Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements (1)
            2. 7.9.4.2.5.2 eQEP Switching Characteristics
          6. 7.9.4.2.6 ADC Start-of-Conversion Timing
            1. 7.9.4.2.6.1 External ADC Start-of-Conversion Switching Characteristics
            2. 7.9.4.2.6.2 ADCSOCAO or ADCSOCBO Timing
        3. 7.9.4.3 External Interrupt Timing
          1. 7.9.4.3.1 External Interrupt Timing Requirements (1)
          2. 7.9.4.3.2 External Interrupt Switching Characteristics (1)
          3. 7.9.4.3.3 External Interrupt Timing Diagram
        4. 7.9.4.4 I2C Electrical Specification and Timing
          1. 7.9.4.4.1 I2C Timing
        5. 7.9.4.5 Serial Peripheral Interface (SPI) Timing
          1. 7.9.4.5.1 Master Mode Timing
            1. 7.9.4.5.1.1 SPI Master Mode External Timing (Clock Phase = 0) (1) (1) (1) (1) (1)
            2. 7.9.4.5.1.2 SPI Master Mode External Timing (Clock Phase = 1) (1) (1) (1) (1) (1)
          2. 7.9.4.5.2 Slave Mode Timing
            1. 7.9.4.5.2.1 SPI Slave Mode External Timing (Clock Phase = 0) (1) (1) (1) (1) (1)
            2. 7.9.4.5.2.2 SPI Slave Mode External Timing (Clock Phase = 1) (1) (1) (1) (1)
        6. 7.9.4.6 Multichannel Buffered Serial Port (McBSP) Timing
          1. 7.9.4.6.1 McBSP Transmit and Receive Timing
            1. 7.9.4.6.1.1 McBSP Timing Requirements (1) (1)
            2. 7.9.4.6.1.2 McBSP Switching Characteristics (1) (1)
          2. 7.9.4.6.2 McBSP as SPI Master or Slave Timing
            1. 7.9.4.6.2.1 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0) (1)
            2. 7.9.4.6.2.2 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)
            3. 7.9.4.6.2.3 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0) (1)
            4. 7.9.4.6.2.4 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)
            5. 7.9.4.6.2.5 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1) (1)
            6. 7.9.4.6.2.6 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)
            7. 7.9.4.6.2.7 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1) (1)
            8. 7.9.4.6.2.8 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1) (1)
      5. 7.9.5 Emulator Connection Without Signal Buffering for the MCU
      6. 7.9.6 External Interface (XINTF) Timing
        1. 7.9.6.1 USEREADY = 0
        2. 7.9.6.2 Synchronous Mode (USEREADY = 1, READYMODE = 0)
        3. 7.9.6.3 Asynchronous Mode (USEREADY = 1, READYMODE = 1)
        4. 7.9.6.4 XINTF Signal Alignment to XCLKOUT
        5. 7.9.6.5 External Interface Read Timing
          1. 7.9.6.5.1 External Interface Read Timing Requirements
          2. 7.9.6.5.2 External Interface Read Switching Characteristics
        6. 7.9.6.6 External Interface Write Timing
          1. 7.9.6.6.1 External Interface Write Switching Characteristics
        7. 7.9.6.7 External Interface Ready-on-Read Timing With One External Wait State
          1. 7.9.6.7.1 External Interface Read Switching Characteristics (Ready-on-Read, One Wait State)
          2. 7.9.6.7.2 External Interface Read Timing Requirements (Ready-on-Read, One Wait State)
          3. 7.9.6.7.3 Synchronous XREADY Timing Requirements (Ready-on-Read, One Wait State) (1)
          4. 7.9.6.7.4 Asynchronous XREADY Timing Requirements (Ready-on-Read, One Wait State)
        8. 7.9.6.8 External Interface Ready-on-Write Timing With One External Wait State
          1. 7.9.6.8.1 External Interface Write Switching Characteristics (Ready-on-Write, One Wait State)
          2. 7.9.6.8.2 Synchronous XREADY Timing Requirements (Ready-on-Write, One Wait State) Table 1-1
          3. 7.9.6.8.3 Asynchronous XREADY Timing Requirements (Ready-on-Write, One Wait State) (1)
        9. 7.9.6.9 XHOLD and XHOLDA Timing
          1. 7.9.6.9.1 XHOLD/ XHOLDA Timing Requirements (1) (1) (1)
  8. 8 Detailed Description
    1. 8.1 Brief Descriptions
      1. 8.1.1  C28x CPU
      2. 8.1.2  Memory Bus (Harvard Bus Architecture)
      3. 8.1.3  Peripheral Bus
      4. 8.1.4  Real-Time JTAG and Analysis
      5. 8.1.5  External Interface (XINTF)
      6. 8.1.6  M0, M1 SARAMs
      7. 8.1.7  L0, L1, L2, L3, L4, L5, L6, L7, H0, H1, H2, H3, H4, H5 SARAMs
      8. 8.1.8  Boot ROM
      9. 8.1.9  Security
      10. 8.1.10 Peripheral Interrupt Expansion (PIE) Block
      11. 8.1.11 External Interrupts (XINT1–XINT7, XNMI)
      12. 8.1.12 Oscillator and PLL
      13. 8.1.13 Watchdog
      14. 8.1.14 Peripheral Clocking
      15. 8.1.15 Low-Power Modes
      16. 8.1.16 Peripheral Frames 0, 1, 2, 3 (PFn)
      17. 8.1.17 General-Purpose Input/Output (GPIO) Multiplexer
      18. 8.1.18 32-Bit CPU-Timers (0, 1, 2)
      19. 8.1.19 Control Peripherals
      20. 8.1.20 Serial Port Peripherals
    2. 8.2 Peripherals
      1. 8.2.1  DMA Overview
      2. 8.2.2  32-Bit CPU-Timer 0, CPU-Timer 1, CPU-Timer 2
      3. 8.2.3  Enhanced PWM Modules
      4. 8.2.4  High-Resolution PWM (HRPWM)
      5. 8.2.5  Enhanced CAP Modules
      6. 8.2.6  Enhanced QEP Modules
      7. 8.2.7  External ADC Interface
      8. 8.2.8  Multichannel Buffered Serial Port (McBSP) Module
      9. 8.2.9  Enhanced Controller Area Network (eCAN) Modules (eCAN-A and eCAN-B)
      10. 8.2.10 Serial Communications Interface (SCI) Modules (SCI-A, SCI-B, SCI-C)
      11. 8.2.11 Serial Peripheral Interface (SPI) Module (SPI-A, SPI-D)
      12. 8.2.12 Inter-Integrated Circuit (I2C)
      13. 8.2.13 GPIO MUX
      14. 8.2.14 External Interface (XINTF)
    3. 8.3 Memory Maps
    4. 8.4 Register Map
      1. 8.4.1 Device Emulation Registers
    5. 8.5 Interrupts
      1. 8.5.1 External Interrupts
    6. 8.6 System Control
      1. 8.6.1 OSC and PLL Block
        1. 8.6.1.1 External Reference Oscillator Clock Option
        2. 8.6.1.2 PLL-Based Clock Module
        3. 8.6.1.3 Loss of Input Clock
      2. 8.6.2 Watchdog Block
    7. 8.7 Low-Power Modes Block
  9. 9 Applications, Implementation, and Layout
    1. 9.1 TI Design or Reference Design
  10. 10Device and Documentation Support
    1. 10.1 Getting Started
    2. 10.2 Device and Development Support Tool Nomenclature
    3. 10.3 Tools and Software
    4. 10.4 Documentation Support
    5. 10.5 支持资源
    6. 10.6 Trademarks
    7. 10.7 静电放电警告
    8. 10.8 术语表
  11. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

封装选项

机械数据 (封装 | 引脚)
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7.9.6.5.2 External Interface Read Switching Characteristics
PARAMETERMINMAXUNIT
td(XCOH-XZCSL)Delay time, XCLKOUT high to zone chip-select active low02ns
td(XCOHL-XZCSH)Delay time, XCLKOUT high/low to zone chip-select inactive high–0.20.9ns
td(XCOH-XA)Delay time, XCLKOUT high to address valid1.5ns
td(XCOHL-XRDL)Delay time, XCLKOUT high/low to XRD active low–0.20.8ns
td(XCOHL-XRDH)Delay time, XCLKOUT high/low to XRD inactive high–0.40.8ns
th(XA)XZCSHHold time, address valid after zone chip-select inactive high (1)ns
th(XA)XRDHold time, address valid after XRD inactive high var tempcontentStr='/Analog & Mixed-Signal/microcontrollers (mcus) & processors/c2000 real-time microcontrollers'; var partNum ='TMS320C28342'; var contentStr = replaceSplChars( tempcontentStr )+ "/"+ partNum; var tiContentGroup = contentStr.replace("'",""); function replaceSplChars(content){ var myRegExp=new RegExp("™|®|™","gi"); content=content.replace(myRegExp,""); return content; } var tiProductPathID='/4/5014/'; var tiPageName = 'Literature reader-ZHCSA18F-zh_CN'; var tiDocType = 'Data Sheet'; var tiLibraryStore = new com.TI.tiLibrary.tiLibraryStore(); var tiLibraryViewerStore = tiLibraryStore.viewer_store; RiotControl.addStore(tiLibraryStore); var subRoutes = riot.route.create(); subRoutes("/document-viewer/*/datasheet/*\\?*#*", function(gpn, url, params, anchor) { RiotControl.trigger("ti_library_open_viewer", { document: tiLibraryViewerStore.document, documentLocale: tiLibraryViewerStore.documentLocale, url: "/document-viewer/" + gpn + "/datasheet/" + url + "#" + anchor, toc: true, set_content: true }); }); subRoutes("/document-viewer/*/datasheet/*#*", function(gpn, url, anchor) { RiotControl.trigger("ti_library_open_viewer", { document: tiLibraryViewerStore.document, documentLocale: tiLibraryViewerStore.documentLocale, url: "/document-viewer/" + gpn + "/datasheet/" + url + "#" + anchor, toc: true, set_content: true }); }); subRoutes("/document-viewer/*/datasheet/*", function(gpn, url) { RiotControl.trigger("ti_library_open_viewer", { document: tiLibraryViewerStore.document, documentLocale: tiLibraryViewerStore.documentLocale, url: "/document-viewer/" + gpn + "/datasheet/" + url, toc: true, set_content: true }); }); subRoutes("/document-viewer/*/*/datasheet/*\\?*#*", function(locale, gpn, url, params, anchor) { RiotControl.trigger("ti_library_open_viewer", { document: tiLibraryViewerStore.document, documentLocale: tiLibraryViewerStore.documentLocale, url: "/document-viewer/" + locale + "/" + gpn + "/datasheet/" + url + "#" + anchor, toc: true, set_content: true }); }); subRoutes("/document-viewer/*/*/datasheet/*#*", function(locale, gpn, url, anchor) { RiotControl.trigger("ti_library_open_viewer", { document: tiLibraryViewerStore.document, documentLocale: tiLibraryViewerStore.documentLocale, url: "/document-viewer/" + locale + "/" + gpn + "/datasheet/" + url + "#" + anchor, toc: true, set_content: true }); }); subRoutes("/document-viewer/*/*/datasheet/*", function(locale, gpn, url) { RiotControl.trigger("ti_library_open_viewer", { document: tiLibraryViewerStore.document, documentLocale: tiLibraryViewerStore.documentLocale, url: "/document-viewer/" + locale + "/" + gpn + "/datasheet/" + url, toc: true, set_content: true }); }); subRoutes("/document-viewer/*/datasheet#*/*", function(gpn, url, fragment) { RiotControl.trigger("ti_library_open_viewer", { document: tiLibraryViewerStore.document, documentLocale: tiLibraryViewerStore.documentLocale, url: "/document-viewer/" + gpn + "/datasheet#" + url + "/" + fragment, toc: true, set_content: true }); }); subRoutes("/document-viewer/*/*/datasheet#*/*", function(locale, gpn, url, fragment) { RiotControl.trigger("ti_library_open_viewer", { document: tiLibraryViewerStore.document, documentLocale: tiLibraryViewerStore.documentLocale, url: "/document-viewer/" + locale + "/" + gpn + "/datasheet#" + url + "/" + fragment, toc: true, set_content: true }); }); subRoutes("/document-viewer/lit/html/*", function(litnum) { RiotControl.trigger("ti_library_open_viewer", { document: tiLibraryViewerStore.document, documentLocale: tiLibraryViewerStore.documentLocale, url: "/document-viewer/lit/html/" + litnum, toc: true, set_content: true }); }); subRoutes("/document-viewer/lit/html/*/*\\?*#*", function(litnum, url, params, anchor) { RiotControl.trigger("ti_library_open_viewer", { document: tiLibraryViewerStore.document, documentLocale: tiLibraryViewerStore.documentLocale, url: "/document-viewer/lit/html/" + litnum + "/" + url + "#" + anchor, toc: true, set_content: true }); }); subRoutes("/document-viewer/lit/html/*/*#*", function(litnum, url, anchor) { RiotControl.trigger("ti_library_open_viewer", { document: tiLibraryViewerStore.document, documentLocale: tiLibraryViewerStore.documentLocale, url: "/document-viewer/lit/html/" + litnum + "/" + url + "#" + anchor, toc: true, set_content: true }); }); subRoutes("/document-viewer/lit/html/*#*/*", function(litnum, url, anchor) { RiotControl.trigger("ti_library_open_viewer", { document: tiLibraryViewerStore.document, documentLocale: tiLibraryViewerStore.documentLocale, url: "/document-viewer/lit/html/" + litnum + "#" + url + "/" + anchor, toc: true, set_content: true }); }); subRoutes("/document-viewer/*/lit/html/*#*/*", function(locale, litnum, url, anchor) { RiotControl.trigger("ti_library_open_viewer", { document: tiLibraryViewerStore.document, documentLocale: tiLibraryViewerStore.documentLocale, url: "/document-viewer/" + locale + "/lit/html/" + litnum + "#" + url + "/" + anchor, toc: true, set_content: true }); }); subRoutes("/document-viewer/lit/html/*/*", function(litnum, url) { RiotControl.trigger("ti_library_open_viewer", { document: tiLibraryViewerStore.document, documentLocale: tiLibraryViewerStore.documentLocale, url: "/document-viewer/lit/html/" + litnum + "/" + url, toc: true, set_content: true }); }); subRoutes("/document-viewer/*/lit/html/*/*\\?*#*", function(locale, litnum, url, params, anchor) { RiotControl.trigger("ti_library_open_viewer", { document: tiLibraryViewerStore.document, documentLocale: tiLibraryViewerStore.documentLocale, url: "/document-viewer/" + locale + "/lit/html/" + litnum + "/" + url + "#" + anchor, toc: true, set_content: true }); }); subRoutes("/document-viewer/*/lit/html/*/*#*", function(locale, litnum, url, anchor) { RiotControl.trigger("ti_library_open_viewer", { document: tiLibraryViewerStore.document, documentLocale: tiLibraryViewerStore.documentLocale, url: "/document-viewer/" + locale + "/lit/html/" + litnum + "/" + url + "#" + anchor, toc: true, set_content: true }); }); subRoutes("/document-viewer/*/lit/html/*/*", function(locale, litnum, url) { RiotControl.trigger("ti_library_open_viewer", { document: tiLibraryViewerStore.document, documentLocale: tiLibraryViewerStore.documentLocale, url: "/document-viewer/" + locale + "/lit/html/" + litnum + "/" + url, toc: true, set_content: true }); }); var compose_url = function(q) { //URL format: scheme:[//[user[:password]@]host[:port]][/path][?query][#fragment] var tempUrl = q.url.replace("//www.yogichopra.com/", ""); var url = tempUrl.replace("//www.yogichopra.com/", ""); if (q.search != null) { var params = ""; var hash = ""; var url_parts = url.split('#'); if (url_parts.length == 2) { url = url_parts[0]; hash = url_parts[1]; } var param_parts = url.split('?'); if (param_parts.length == 2) { url = param_parts[0]; var parsed_params = param_parts[1].split('&'); var keyword_param_found = false; for (var i = 0; i < parsed_params.length; i++) { if (parsed_params[i].indexOf('search=') == 0) { keyword_param_found = true; parsed_params[i] = 'search=' + q.search; } } if (!keyword_param_found) { parsed_params.push('search=' + q.search); } params = parsed_params.join('&'); } else { params = 'search=' + q.search; } if (params > "") { url = url + '?' + params; } if (hash > "") { url = url + '#' + hash; } } return url; }; tiLibraryViewerStore.compose_url_route = function(location, q) { return compose_url(q); }; tiLibraryViewerStore.compute_content_href = function(href, url) { return url; }; tiLibraryViewerStore.compose_topic_url = function(location, q) { return compose_url(q); }; tiLibraryViewerStore.important_notice_url = "//www.yogichopra.com/document-viewer/cn/TMS320C28342/datasheet/important_notice#ImpNotice001"; var ods_reader = riot.mount('ti-library-viewer', { store: tiLibraryStore.list_store, viewerstore: tiLibraryViewerStore }); riot.route.base('/'); riot.route.start(true); compute_document_locale = function(docName) { var locale = 'en_US'; if (docName) { if (docName.toLowerCase().indexOf('z')===0) { locale = 'zh_CN'; } else if (docName.toLowerCase().indexOf('j') == 0) { locale = 'ja_JP'; } } return locale; } open_reader = function() { var path = window.location.pathname.split('/'); var path_minus_filename = ''; for (var i = 0; i < path.length - 1; i++) { if (i == 0 && path[i] == '') { console.log("double slashes found in beginning of document path; treating document path as local machine path"); continue; } path_minus_filename += "/" + path[i]; } RiotControl.trigger("ti_library_open_viewer", { documentLocale: compute_document_locale( "ZHCSA18F"), document: { href: path_minus_filename, lit_num: "ZHCSA18F", doc_type: "Data Sheet", show_toc: "true", translated_doc_type: "数据表", gpn: "TMS320C28342", title: "TMS320F2833x、TMS320F2823x 数字信号控制器 (DSC)TMS320C2834x Delfino 微控制器", disclaimer: "本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。 ", product: "//www.yogichopra.com/product/cn/TMS320C28342", email: 'mailto:?subject=TMS320C28342 Datasheet&body=/document-viewer/cn/TMS320C28342/datasheet', download: '//www.yogichopra.com/cn/lit/gpn/TMS320C28342', tistore: '//store.ti.com/Search.aspx?k=TMS320C28342&pt=-1', productstatusdescription: 'PRODUCTION DATA' }, url: "/document-viewer/cn/TMS320C28342/datasheet/GUID-B1283752-8D92-4850-A9D5-FC8F401847AC", prepopulated: true, modalOptions: { dismissible: false } }); } open_reader();
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