ZHCSA18F March   2009  – February 2021 TMS320C28341 , TMS320C28342 , TMS320C28343 , TMS320C28343-Q1 , TMS320C28344 , TMS320C28345 , TMS320C28346 , TMS320C28346-Q1

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1. 3.1 Functional Block Diagram
  4. 4 Revision History
  5. 5 Device Comparison
    1. 5.1 Related Products
  6. 6 Terminal Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Signal Descriptions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings (1) (1)
    2. 7.2 ESD Ratings – Automotive
    3. 7.3 ESD Ratings – Commercial
    4. 7.4 Recommended Operating Conditions
    5. 7.5 Power Consumption Summary
      1. 7.5.1 TMS320C28346/C28344 (1) Current Consumption by Power-Supply Pins at 300-MHz SYSCLKOUT
      2. 7.5.2 TMS320C28345/C28343 (1) Current Consumption by Power-Supply Pins at 200-MHz SYSCLKOUT
      3. 7.5.3 Reducing Current Consumption
    6. 7.6 Electrical Characteristics
    7. 7.7 Thermal Resistance Characteristics
      1. 7.7.1 ZHH Package
      2. 7.7.2 ZFE Package
    8. 7.8 Thermal Design Considerations
    9. 7.9 Timing and Switching Characteristics
      1. 7.9.1 Timing Parameter Symbology
        1. 7.9.1.1 General Notes on Timing Parameters
        2. 7.9.1.2 Test Load Circuit
        3. 7.9.1.3 Device Clock Table
          1. 7.9.1.3.1 Clocking and Nomenclature (300-MHz Devices)
          2. 7.9.1.3.2 Clocking and Nomenclature (200-MHz Devices)
      2. 7.9.2 Power Sequencing
        1. 7.9.2.1 Power Management and Supervisory Circuit Solutions
        2. 7.9.2.2 Reset ( XRS) Timing Requirements
      3. 7.9.3 Clock Requirements and Characteristics
        1. 7.9.3.1 XCLKIN/X1 Timing Requirements – PLL Enabled
        2. 7.9.3.2 XCLKIN/X1 Timing Requirements – PLL Disabled
        3. 7.9.3.3 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled) (1) (1)
        4. 7.9.3.4 Timing Diagram
      4. 7.9.4 Peripherals
        1. 7.9.4.1 General-Purpose Input/Output (GPIO)
          1. 7.9.4.1.1 GPIO - Output Timing
            1. 7.9.4.1.1.1 General-Purpose Output Switching Characteristics
          2. 7.9.4.1.2 GPIO - Input Timing
            1. 7.9.4.1.2.1 General-Purpose Input Timing Requirements
          3. 7.9.4.1.3 Sampling Window Width for Input Signals
          4. 7.9.4.1.4 Low-Power Mode Wakeup Timing
            1. 7.9.4.1.4.1 IDLE Mode Timing Requirements (1)
            2. 7.9.4.1.4.2 IDLE Mode Switching Characteristics (1)
            3. 7.9.4.1.4.3 IDLE Mode Timing Diagram
            4. 7.9.4.1.4.4 STANDBY Mode Timing Requirements
            5. 7.9.4.1.4.5 STANDBY Mode Switching Characteristics
            6. 7.9.4.1.4.6 STANDBY Mode Timing Diagram
            7. 7.9.4.1.4.7 HALT Mode Timing Requirements
            8. 7.9.4.1.4.8 HALT Mode Switching Characteristics
            9. 7.9.4.1.4.9 HALT Mode Timing Diagram
        2. 7.9.4.2 Enhanced Control Peripherals
          1. 7.9.4.2.1 Enhanced Pulse Width Modulator (ePWM) Timing
            1. 7.9.4.2.1.1 ePWM Timing Requirements (1)
            2. 7.9.4.2.1.2 ePWM Switching Characteristics
          2. 7.9.4.2.2 Trip-Zone Input Timing
            1. 7.9.4.2.2.1 Trip-Zone Input Timing Requirements (1)
          3. 7.9.4.2.3 High-Resolution PWM Timing
            1. 7.9.4.2.3.1 High-Resolution PWM Characteristics at SYSCLKOUT = (150–300 MHz)
          4. 7.9.4.2.4 Enhanced Capture (eCAP) Timing
            1. 7.9.4.2.4.1 Enhanced Capture (eCAP) Timing Requirements (1)
            2. 7.9.4.2.4.2 eCAP Switching Characteristics
          5. 7.9.4.2.5 Enhanced Quadrature Encoder Pulse (eQEP) Timing
            1. 7.9.4.2.5.1 Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements (1)
            2. 7.9.4.2.5.2 eQEP Switching Characteristics
          6. 7.9.4.2.6 ADC Start-of-Conversion Timing
            1. 7.9.4.2.6.1 External ADC Start-of-Conversion Switching Characteristics
            2. 7.9.4.2.6.2 ADCSOCAO or ADCSOCBO Timing
        3. 7.9.4.3 External Interrupt Timing
          1. 7.9.4.3.1 External Interrupt Timing Requirements (1)
          2. 7.9.4.3.2 External Interrupt Switching Characteristics (1)
          3. 7.9.4.3.3 External Interrupt Timing Diagram
        4. 7.9.4.4 I2C Electrical Specification and Timing
          1. 7.9.4.4.1 I2C Timing
        5. 7.9.4.5 Serial Peripheral Interface (SPI) Timing
          1. 7.9.4.5.1 Master Mode Timing
            1. 7.9.4.5.1.1 SPI Master Mode External Timing (Clock Phase = 0) (1) (1) (1) (1) (1)
            2. 7.9.4.5.1.2 SPI Master Mode External Timing (Clock Phase = 1) (1) (1) (1) (1) (1)
          2. 7.9.4.5.2 Slave Mode Timing
            1. 7.9.4.5.2.1 SPI Slave Mode External Timing (Clock Phase = 0) (1) (1) (1) (1) (1)
            2. 7.9.4.5.2.2 SPI Slave Mode External Timing (Clock Phase = 1) (1) (1) (1) (1)
        6. 7.9.4.6 Multichannel Buffered Serial Port (McBSP) Timing
          1. 7.9.4.6.1 McBSP Transmit and Receive Timing
            1. 7.9.4.6.1.1 McBSP Timing Requirements (1) (1)
            2. 7.9.4.6.1.2 McBSP Switching Characteristics (1) (1)
          2. 7.9.4.6.2 McBSP as SPI Master or Slave Timing
            1. 7.9.4.6.2.1 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0) (1)
            2. 7.9.4.6.2.2 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)
            3. 7.9.4.6.2.3 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0) (1)
            4. 7.9.4.6.2.4 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)
            5. 7.9.4.6.2.5 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1) (1)
            6. 7.9.4.6.2.6 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)
            7. 7.9.4.6.2.7 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1) (1)
            8. 7.9.4.6.2.8 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1) (1)
      5. 7.9.5 Emulator Connection Without Signal Buffering for the MCU
      6. 7.9.6 External Interface (XINTF) Timing
        1. 7.9.6.1 USEREADY = 0
        2. 7.9.6.2 Synchronous Mode (USEREADY = 1, READYMODE = 0)
        3. 7.9.6.3 Asynchronous Mode (USEREADY = 1, READYMODE = 1)
        4. 7.9.6.4 XINTF Signal Alignment to XCLKOUT
        5. 7.9.6.5 External Interface Read Timing
          1. 7.9.6.5.1 External Interface Read Timing Requirements
          2. 7.9.6.5.2 External Interface Read Switching Characteristics
        6. 7.9.6.6 External Interface Write Timing
          1. 7.9.6.6.1 External Interface Write Switching Characteristics
        7. 7.9.6.7 External Interface Ready-on-Read Timing With One External Wait State
          1. 7.9.6.7.1 External Interface Read Switching Characteristics (Ready-on-Read, One Wait State)
          2. 7.9.6.7.2 External Interface Read Timing Requirements (Ready-on-Read, One Wait State)
          3. 7.9.6.7.3 Synchronous XREADY Timing Requirements (Ready-on-Read, One Wait State) (1)
          4. 7.9.6.7.4 Asynchronous XREADY Timing Requirements (Ready-on-Read, One Wait State)
        8. 7.9.6.8 External Interface Ready-on-Write Timing With One External Wait State
          1. 7.9.6.8.1 External Interface Write Switching Characteristics (Ready-on-Write, One Wait State)
          2. 7.9.6.8.2 Synchronous XREADY Timing Requirements (Ready-on-Write, One Wait State) Table 1-1
          3. 7.9.6.8.3 Asynchronous XREADY Timing Requirements (Ready-on-Write, One Wait State) (1)
        9. 7.9.6.9 XHOLD and XHOLDA Timing
          1. 7.9.6.9.1 XHOLD/ XHOLDA Timing Requirements (1) (1) (1)
  8. 8 Detailed Description
    1. 8.1 Brief Descriptions
      1. 8.1.1  C28x CPU
      2. 8.1.2  Memory Bus (Harvard Bus Architecture)
      3. 8.1.3  Peripheral Bus
      4. 8.1.4  Real-Time JTAG and Analysis
      5. 8.1.5  External Interface (XINTF)
      6. 8.1.6  M0, M1 SARAMs
      7. 8.1.7  L0, L1, L2, L3, L4, L5, L6, L7, H0, H1, H2, H3, H4, H5 SARAMs
      8. 8.1.8  Boot ROM
      9. 8.1.9  Security
      10. 8.1.10 Peripheral Interrupt Expansion (PIE) Block
      11. 8.1.11 External Interrupts (XINT1–XINT7, XNMI)
      12. 8.1.12 Oscillator and PLL
      13. 8.1.13 Watchdog
      14. 8.1.14 Peripheral Clocking
      15. 8.1.15 Low-Power Modes
      16. 8.1.16 Peripheral Frames 0, 1, 2, 3 (PFn)
      17. 8.1.17 General-Purpose Input/Output (GPIO) Multiplexer
      18. 8.1.18 32-Bit CPU-Timers (0, 1, 2)
      19. 8.1.19 Control Peripherals
      20. 8.1.20 Serial Port Peripherals
    2. 8.2 Peripherals
      1. 8.2.1  DMA Overview
      2. 8.2.2  32-Bit CPU-Timer 0, CPU-Timer 1, CPU-Timer 2
      3. 8.2.3  Enhanced PWM Modules
      4. 8.2.4  High-Resolution PWM (HRPWM)
      5. 8.2.5  Enhanced CAP Modules
      6. 8.2.6  Enhanced QEP Modules
      7. 8.2.7  External ADC Interface
      8. 8.2.8  Multichannel Buffered Serial Port (McBSP) Module
      9. 8.2.9  Enhanced Controller Area Network (eCAN) Modules (eCAN-A and eCAN-B)
      10. 8.2.10 Serial Communications Interface (SCI) Modules (SCI-A, SCI-B, SCI-C)
      11. 8.2.11 Serial Peripheral Interface (SPI) Module (SPI-A, SPI-D)
      12. 8.2.12 Inter-Integrated Circuit (I2C)
      13. 8.2.13 GPIO MUX
      14. 8.2.14 External Interface (XINTF)
    3. 8.3 Memory Maps
    4. 8.4 Register Map
      1. 8.4.1 Device Emulation Registers
    5. 8.5 Interrupts
      1. 8.5.1 External Interrupts
    6. 8.6 System Control
      1. 8.6.1 OSC and PLL Block
        1. 8.6.1.1 External Reference Oscillator Clock Option
        2. 8.6.1.2 PLL-Based Clock Module
        3. 8.6.1.3 Loss of Input Clock
      2. 8.6.2 Watchdog Block
    7. 8.7 Low-Power Modes Block
  9. 9 Applications, Implementation, and Layout
    1. 9.1 TI Design or Reference Design
  10. 10Device and Documentation Support
    1. 10.1 Getting Started
    2. 10.2 Device and Development Support Tool Nomenclature
    3. 10.3 Tools and Software
    4. 10.4 Documentation Support
    5. 10.5 支持资源
    6. 10.6 Trademarks
    7. 10.7 静电放电警告
    8. 10.8 术语表
  11. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.9.6.9 XHOLD and XHOLDA Timing

If the HOLD mode bit is set while XHOLD and XHOLDA are both low (external bus accesses granted), the XHOLDA signal is forced high (at the end of the current cycle) and the external interface is taken out of high-impedance mode.

On a reset ( XRS), the HOLD mode bit is set to 0. If the XHOLD signal is active low on a system reset, the bus and all signal strobes must be in high-impedance mode, and the XHOLDA signal is also driven active low.

When HOLD mode is enabled and XHOLDA is active low (external bus grant active), the CPU can still execute code from internal memory. If an access is made to the external interface, the CPU is stalled until the XHOLD signal is removed.

An external DMA request, when granted, places the following signals in a high-impedance mode:

XA[19:0]XZCS0
XD[31:0], XD[15:0]XZCS6
XWE0, XWE1, XRDXZCS7
XR/ W

All other signals not listed in this group remain in their default or functional operational modes during these signal events.
千亿体育app官网登录(中国)官方网站IOS/安卓通用版/手机APP | 米乐app下载官网（中国）|ios|Android/通用版APP最新版 | 米乐|米乐·M6（中国大陆）官方网站 | 千亿体育登陆地址 | 华体会体育（中国）HTH·官方网站 | 千赢qy国际_全站最新版千赢qy国际V6.2.14安卓/IOS下载 | 18新利网v1.2.5|中国官方网站 | bob电竞真人（中国官网）安卓/ios苹果/电脑版【1.97.95版下载】 | 千亿体育app官方下载(中国)官方网站IOS/安卓/手机APP下载安装 |