ZHCSA18F March   2009  – February 2021 TMS320C28341 , TMS320C28342 , TMS320C28343 , TMS320C28343-Q1 , TMS320C28344 , TMS320C28345 , TMS320C28346 , TMS320C28346-Q1

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1. 3.1 Functional Block Diagram
  4. 4 Revision History
  5. 5 Device Comparison
    1. 5.1 Related Products
  6. 6 Terminal Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Signal Descriptions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings (1) (1)
    2. 7.2 ESD Ratings – Automotive
    3. 7.3 ESD Ratings – Commercial
    4. 7.4 Recommended Operating Conditions
    5. 7.5 Power Consumption Summary
      1. 7.5.1 TMS320C28346/C28344 (1) Current Consumption by Power-Supply Pins at 300-MHz SYSCLKOUT
      2. 7.5.2 TMS320C28345/C28343 (1) Current Consumption by Power-Supply Pins at 200-MHz SYSCLKOUT
      3. 7.5.3 Reducing Current Consumption
    6. 7.6 Electrical Characteristics
    7. 7.7 Thermal Resistance Characteristics
      1. 7.7.1 ZHH Package
      2. 7.7.2 ZFE Package
    8. 7.8 Thermal Design Considerations
    9. 7.9 Timing and Switching Characteristics
      1. 7.9.1 Timing Parameter Symbology
        1. 7.9.1.1 General Notes on Timing Parameters
        2. 7.9.1.2 Test Load Circuit
        3. 7.9.1.3 Device Clock Table
          1. 7.9.1.3.1 Clocking and Nomenclature (300-MHz Devices)
          2. 7.9.1.3.2 Clocking and Nomenclature (200-MHz Devices)
      2. 7.9.2 Power Sequencing
        1. 7.9.2.1 Power Management and Supervisory Circuit Solutions
        2. 7.9.2.2 Reset ( XRS) Timing Requirements
      3. 7.9.3 Clock Requirements and Characteristics
        1. 7.9.3.1 XCLKIN/X1 Timing Requirements – PLL Enabled
        2. 7.9.3.2 XCLKIN/X1 Timing Requirements – PLL Disabled
        3. 7.9.3.3 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled) (1) (1)
        4. 7.9.3.4 Timing Diagram
      4. 7.9.4 Peripherals
        1. 7.9.4.1 General-Purpose Input/Output (GPIO)
          1. 7.9.4.1.1 GPIO - Output Timing
            1. 7.9.4.1.1.1 General-Purpose Output Switching Characteristics
          2. 7.9.4.1.2 GPIO - Input Timing
            1. 7.9.4.1.2.1 General-Purpose Input Timing Requirements
          3. 7.9.4.1.3 Sampling Window Width for Input Signals
          4. 7.9.4.1.4 Low-Power Mode Wakeup Timing
            1. 7.9.4.1.4.1 IDLE Mode Timing Requirements (1)
            2. 7.9.4.1.4.2 IDLE Mode Switching Characteristics (1)
            3. 7.9.4.1.4.3 IDLE Mode Timing Diagram
            4. 7.9.4.1.4.4 STANDBY Mode Timing Requirements
            5. 7.9.4.1.4.5 STANDBY Mode Switching Characteristics
            6. 7.9.4.1.4.6 STANDBY Mode Timing Diagram
            7. 7.9.4.1.4.7 HALT Mode Timing Requirements
            8. 7.9.4.1.4.8 HALT Mode Switching Characteristics
            9. 7.9.4.1.4.9 HALT Mode Timing Diagram
        2. 7.9.4.2 Enhanced Control Peripherals
          1. 7.9.4.2.1 Enhanced Pulse Width Modulator (ePWM) Timing
            1. 7.9.4.2.1.1 ePWM Timing Requirements (1)
            2. 7.9.4.2.1.2 ePWM Switching Characteristics
          2. 7.9.4.2.2 Trip-Zone Input Timing
            1. 7.9.4.2.2.1 Trip-Zone Input Timing Requirements (1)
          3. 7.9.4.2.3 High-Resolution PWM Timing
            1. 7.9.4.2.3.1 High-Resolution PWM Characteristics at SYSCLKOUT = (150–300 MHz)
          4. 7.9.4.2.4 Enhanced Capture (eCAP) Timing
            1. 7.9.4.2.4.1 Enhanced Capture (eCAP) Timing Requirements (1)
            2. 7.9.4.2.4.2 eCAP Switching Characteristics
          5. 7.9.4.2.5 Enhanced Quadrature Encoder Pulse (eQEP) Timing
            1. 7.9.4.2.5.1 Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements (1)
            2. 7.9.4.2.5.2 eQEP Switching Characteristics
          6. 7.9.4.2.6 ADC Start-of-Conversion Timing
            1. 7.9.4.2.6.1 External ADC Start-of-Conversion Switching Characteristics
            2. 7.9.4.2.6.2 ADCSOCAO or ADCSOCBO Timing
        3. 7.9.4.3 External Interrupt Timing
          1. 7.9.4.3.1 External Interrupt Timing Requirements (1)
          2. 7.9.4.3.2 External Interrupt Switching Characteristics (1)
          3. 7.9.4.3.3 External Interrupt Timing Diagram
        4. 7.9.4.4 I2C Electrical Specification and Timing
          1. 7.9.4.4.1 I2C Timing
        5. 7.9.4.5 Serial Peripheral Interface (SPI) Timing
          1. 7.9.4.5.1 Master Mode Timing
            1. 7.9.4.5.1.1 SPI Master Mode External Timing (Clock Phase = 0) (1) (1) (1) (1) (1)
            2. 7.9.4.5.1.2 SPI Master Mode External Timing (Clock Phase = 1) (1) (1) (1) (1) (1)
          2. 7.9.4.5.2 Slave Mode Timing
            1. 7.9.4.5.2.1 SPI Slave Mode External Timing (Clock Phase = 0) (1) (1) (1) (1) (1)
            2. 7.9.4.5.2.2 SPI Slave Mode External Timing (Clock Phase = 1) (1) (1) (1) (1)
        6. 7.9.4.6 Multichannel Buffered Serial Port (McBSP) Timing
          1. 7.9.4.6.1 McBSP Transmit and Receive Timing
            1. 7.9.4.6.1.1 McBSP Timing Requirements (1) (1)
            2. 7.9.4.6.1.2 McBSP Switching Characteristics (1) (1)
          2. 7.9.4.6.2 McBSP as SPI Master or Slave Timing
            1. 7.9.4.6.2.1 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0) (1)
            2. 7.9.4.6.2.2 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)
            3. 7.9.4.6.2.3 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0) (1)
            4. 7.9.4.6.2.4 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)
            5. 7.9.4.6.2.5 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1) (1)
            6. 7.9.4.6.2.6 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)
            7. 7.9.4.6.2.7 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1) (1)
            8. 7.9.4.6.2.8 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1) (1)
      5. 7.9.5 Emulator Connection Without Signal Buffering for the MCU
      6. 7.9.6 External Interface (XINTF) Timing
        1. 7.9.6.1 USEREADY = 0
        2. 7.9.6.2 Synchronous Mode (USEREADY = 1, READYMODE = 0)
        3. 7.9.6.3 Asynchronous Mode (USEREADY = 1, READYMODE = 1)
        4. 7.9.6.4 XINTF Signal Alignment to XCLKOUT
        5. 7.9.6.5 External Interface Read Timing
          1. 7.9.6.5.1 External Interface Read Timing Requirements
          2. 7.9.6.5.2 External Interface Read Switching Characteristics
        6. 7.9.6.6 External Interface Write Timing
          1. 7.9.6.6.1 External Interface Write Switching Characteristics
        7. 7.9.6.7 External Interface Ready-on-Read Timing With One External Wait State
          1. 7.9.6.7.1 External Interface Read Switching Characteristics (Ready-on-Read, One Wait State)
          2. 7.9.6.7.2 External Interface Read Timing Requirements (Ready-on-Read, One Wait State)
          3. 7.9.6.7.3 Synchronous XREADY Timing Requirements (Ready-on-Read, One Wait State) (1)
          4. 7.9.6.7.4 Asynchronous XREADY Timing Requirements (Ready-on-Read, One Wait State)
        8. 7.9.6.8 External Interface Ready-on-Write Timing With One External Wait State
          1. 7.9.6.8.1 External Interface Write Switching Characteristics (Ready-on-Write, One Wait State)
          2. 7.9.6.8.2 Synchronous XREADY Timing Requirements (Ready-on-Write, One Wait State) Table 1-1
          3. 7.9.6.8.3 Asynchronous XREADY Timing Requirements (Ready-on-Write, One Wait State) (1)
        9. 7.9.6.9 XHOLD and XHOLDA Timing
          1. 7.9.6.9.1 XHOLD/ XHOLDA Timing Requirements (1) (1) (1)
  8. 8 Detailed Description
    1. 8.1 Brief Descriptions
      1. 8.1.1  C28x CPU
      2. 8.1.2  Memory Bus (Harvard Bus Architecture)
      3. 8.1.3  Peripheral Bus
      4. 8.1.4  Real-Time JTAG and Analysis
      5. 8.1.5  External Interface (XINTF)
      6. 8.1.6  M0, M1 SARAMs
      7. 8.1.7  L0, L1, L2, L3, L4, L5, L6, L7, H0, H1, H2, H3, H4, H5 SARAMs
      8. 8.1.8  Boot ROM
      9. 8.1.9  Security
      10. 8.1.10 Peripheral Interrupt Expansion (PIE) Block
      11. 8.1.11 External Interrupts (XINT1–XINT7, XNMI)
      12. 8.1.12 Oscillator and PLL
      13. 8.1.13 Watchdog
      14. 8.1.14 Peripheral Clocking
      15. 8.1.15 Low-Power Modes
      16. 8.1.16 Peripheral Frames 0, 1, 2, 3 (PFn)
      17. 8.1.17 General-Purpose Input/Output (GPIO) Multiplexer
      18. 8.1.18 32-Bit CPU-Timers (0, 1, 2)
      19. 8.1.19 Control Peripherals
      20. 8.1.20 Serial Port Peripherals
    2. 8.2 Peripherals
      1. 8.2.1  DMA Overview
      2. 8.2.2  32-Bit CPU-Timer 0, CPU-Timer 1, CPU-Timer 2
      3. 8.2.3  Enhanced PWM Modules
      4. 8.2.4  High-Resolution PWM (HRPWM)
      5. 8.2.5  Enhanced CAP Modules
      6. 8.2.6  Enhanced QEP Modules
      7. 8.2.7  External ADC Interface
      8. 8.2.8  Multichannel Buffered Serial Port (McBSP) Module
      9. 8.2.9  Enhanced Controller Area Network (eCAN) Modules (eCAN-A and eCAN-B)
      10. 8.2.10 Serial Communications Interface (SCI) Modules (SCI-A, SCI-B, SCI-C)
      11. 8.2.11 Serial Peripheral Interface (SPI) Module (SPI-A, SPI-D)
      12. 8.2.12 Inter-Integrated Circuit (I2C)
      13. 8.2.13 GPIO MUX
      14. 8.2.14 External Interface (XINTF)
    3. 8.3 Memory Maps
    4. 8.4 Register Map
      1. 8.4.1 Device Emulation Registers
    5. 8.5 Interrupts
      1. 8.5.1 External Interrupts
    6. 8.6 System Control
      1. 8.6.1 OSC and PLL Block
        1. 8.6.1.1 External Reference Oscillator Clock Option
        2. 8.6.1.2 PLL-Based Clock Module
        3. 8.6.1.3 Loss of Input Clock
      2. 8.6.2 Watchdog Block
    7. 8.7 Low-Power Modes Block
  9. 9 Applications, Implementation, and Layout
    1. 9.1 TI Design or Reference Design
  10. 10Device and Documentation Support
    1. 10.1 Getting Started
    2. 10.2 Device and Development Support Tool Nomenclature
    3. 10.3 Tools and Software
    4. 10.4 Documentation Support
    5. 10.5 支持资源
    6. 10.6 Trademarks
    7. 10.7 静电放电警告
    8. 10.8 术语表
  11. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

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6.2 Signal Descriptions

Table 6-1 describes the signals. The GPIO function (shown in Italics) is the default at reset. The peripheral signals that are listed under them are alternate functions. Some peripheral functions may not be available in all devices. See Table 5-1 for details. Inputs are not 5-V tolerant. All XINTF pins have a drive strength of 4 mA (typical). All GPIO pins are I/O/Z, 4-mA drive typical and have an internal pullup, which can be selectively enabled or disabled on a per-pin basis. This feature only applies to the GPIO pins. The pullups on GPIO0–GPIO11 and GPIO58–GPIO63 pins are not enabled at reset. The pullups on GPIO12–GPIO57 and GPIO64–GPIO87 are enabled upon reset.

Table 6-1 Signal Descriptions
NAMEZHH
BALL #		ZFE
BALL #		DESCRIPTION
JTAG
TRSTM7R8JTAG test reset with internal pulldown. TRST, when driven high, gives the scan system control of the operations of the device. If this signal is not connected or driven low, the device operates in its functional mode, and the test reset signals are ignored.
NOTE: TRST is an active high test pin and must be maintained low at all times during normal device operation. An external pulldown resistor is recommended on this pin. The value of this resistor should be based on drive strength of the debugger pods applicable to the design. A 2.2-kΩ resistor generally offers adequate protection. Because this is application-specific, TI recommends validating each target board for proper operation of the debugger and the application. (I, ↓)
TCKP9T11JTAG test clock. An external pullup resistor is required on this pin. A 2.2-kΩ resistor generally offers adequate protection.(I)
TMSM8P9JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAP controller on the rising edge of TCK. (I, ↑)
TDIL6T8JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register (instruction or data) on a rising edge of TCK. (I, ↑)
TDON7P8JTAG scan out, test data output (TDO). The contents of the selected register (instruction or data) are shifted out of TDO on the falling edge of TCK.
EMU0N9P10Emulator pin 0. When TRST is driven high, this pin is used as an interrupt to or from the emulator system and is defined as input/output through the JTAG scan. This pin is also used to put the device into boundary-scan mode. With the EMU0 pin at a logic-high state and the EMU1 pin at a logic-low state, a rising edge on the TRST pin would latch the device into boundary-scan mode.
NOTE: An external pullup resistor is recommended on this pin. The value of this resistor should be based on the drive strength of the debugger pods applicable to the design. A 2.2-kΩ to 4.7-kΩ resistor is generally adequate. Because this is application-specific, TI recommends validating each each target board for proper operation of the debugger and the application.
EMU1L9R10Emulator pin 1. When TRST is driven high, this pin is used as an interrupt to or from the emulator system and is defined as input/output through the JTAG scan. This pin is also used to put the device into boundary-scan mode. With the EMU0 pin at a logic-high state and the EMU1 pin at a logic-low state, a rising edge on the TRST pin would latch the device into boundary-scan mode.
NOTE: An external pullup resistor is recommended on this pin. The value of this resistor should be based on the drive strength of the debugger pods applicable to the design. A 2.2-kΩ to 4.7-kΩ resistor is generally adequate. Because this is application-specific, TI recommends validating each target board for proper operation of the debugger and the application.
Clock
XCLKOUTB14D16Output clock derived from SYSCLKOUT. XCLKOUT is either the same frequency, one-half the frequency, one-fourth the frequency, or one-eighth the frequency of SYSCLKOUT. This is controlled by bit 19 (BY4CLKMODE), bits 18:16 (XTIMCLK), and bit 2 (CLKMODE) in the XINTCNF2 register. At reset, XCLKOUT = SYSCLKOUT/8. The XCLKOUT signal can be turned off by setting XINTCNF2[CLKOFF] to 1. Unlike other GPIO pins, the XCLKOUT pin is not placed in high-impedance state during a reset.
XCLKIND9A12External Oscillator Input. This pin is to feed a clock from an external 3.3-V oscillator. In this case, the X1 pin must be tied to VSSK. If a crystal/resonator is used (or if an external 1.8-V oscillator is used to feed clock to X1 pin), this pin must be tied to VSS. (I)
X1C8A7Internal/External Oscillator Input. To use the internal oscillator, a quartz crystal may be connected across X1 and X2. The X1 pin is referenced to the 1.8-V core digital power supply. A 1.8-V external oscillator may be connected to the X1 pin. In this case, the XCLKIN pin must be connected to VSS. If a 3.3-V external oscillator is used with the XCLKIN pin, X1 must be tied to VSSK. (I)
X2A8A9Internal Oscillator Output. A quartz crystal may be connected across X1 and X2. If X2 is not used it must be left unconnected. (O)
Reset
XRSP8T10Device Reset (in) and Watchdog Reset (out).
Device reset. XRS causes the device to terminate execution. The PC will point to the address contained at the location 0x3FFFC0. When XRS is brought to a high level, execution begins at the location pointed to by the PC. This pin is driven low by the MCU when a watchdog reset occurs. During watchdog reset, the XRS pin is driven low for the watchdog reset duration of 512 OSCCLK cycles. (I/OD, ↑)
The output buffer of this pin is an open drain with an internal pullup. It is recommended that this pin be driven by an open-drain device.
XRSION8T9XRS I/O Control (I) -  This pin must be connected to the XRS pin on the target board. When XRS is low (reset), the level detected on this pin puts all output buffers on the device in high-impedance mode.
External ADC Interface Signals
EXTSOC1AN1M2External ADC SOC Group 1 A Output. Trigger for external ADC, this signal is logical OR of ePWM1/2/3 SOCA internal signals (O)
EXTSOC1BM3M3External ADC SOC Group 1 B Output. Trigger for external ADC, this signal is logical OR of ePWM1/2/3 SOCB internal signals (O)
EXTSOC2AM2N1External ADC SOC Group 2 A Output. Trigger for external ADC, this signal is logical OR of ePWM4/5/6 SOCA internal signals (O)
EXTSOC2BP1N2External ADC SOC Group 2 B Output. Trigger for external ADC, this signal is logical OR of ePWM4/5/6 SOCB internal signals (O)
EXTSOC3AN2N3External ADC SOC Group 3 A Output. Trigger for external ADC, this signal is logical OR of ePWM7/8/9 SOCA internal signals (O)
EXTSOC3BP2P2External ADC SOC Group3 B Output. Trigger for external ADC, this signal is logical OR of ePWM7/8/9 SOCB internal signals (O)
EXTADCCLKN3R3External ADC Clock Signal. Clock for external ADC support, derived from SYSCLK (O)
GPIO and Peripheral Signals
GPIO0
EPWM1A
-
-		B1D2General-purpose input/output 0 (I/O/Z)
Enhanced PWM1 Output A and HRPWM channel (O)
-
-
GPIO1
EPWM1B
ECAP6
MFSRB		C1E1General-purpose input/output 1 (I/O/Z)
Enhanced PWM1 Output B (O)
Enhanced Capture 6 input/output (I/O)
McBSP-B receive frame synch (I/O)
GPIO2
EPWM2A
-
-		F5E2General-purpose input/output 2 (I/O/Z)
Enhanced PWM2 Output A and HRPWM channel (O)
-
-
GPIO3
EPWM2B
ECAP5
MCLKRB		E4E3General-purpose input/output 3 (I/O/Z)
Enhanced PWM2 Output B (O)
Enhanced Capture 5 input/output (I/O)
McBSP-B receive clock (I/O)
GPIO4
EPWM3A
-
-		E2F1General-purpose input/output 4 (I/O/Z)
Enhanced PWM3 output A and HRPWM channel (O)
-
-
GPIO5
EPWM3B
MFSRA
ECAP1		E3F2General-purpose input/output 5 (I/O/Z)
Enhanced PWM3 output B (O)
McBSP-A receive frame synch (I/O)
Enhanced Capture input/output 1 (I/O)
GPIO6
EPWM4A
EPWMSYNCI
EPWMSYNCO		F3F3General-purpose input/output 6 (I/O/Z)
Enhanced PWM4 output A and HRPWM channel (O)
External ePWM sync pulse input (I)
External ePWM sync pulse output (O)
GPIO7
EPWM4B
MCLKRA
ECAP2		F2G1General-purpose input/output 7 (I/O/Z)
Enhanced PWM4 output B (O)
McBSP-A receive clock (I/O)
Enhanced capture input/output 2 (I/O)
GPIO8
EPWM5A
CANTXB
ADCSOCAO		G4G2General-purpose input/output 8 (I/O/Z)
Enhanced PWM5 output A and HRPWM channel (O)
Enhanced CAN-B transmit (O)
ADC start-of-conversion A (O)
GPIO9
EPWM5B
SCITXDB
ECAP3		G2G3General-purpose input/output 9 (I/O/Z)
Enhanced PWM5 output B (O)
SCI-B transmit data(O)
Enhanced capture input/output 3 (I/O)
GPIO10
EPWM6A
CANRXB
ADCSOCBO		G3H1General-purpose input/output 10 (I/O/Z)
Enhanced PWM6 output A and HRPWM channel (O)
Enhanced CAN-B receive (I)
ADC start-of-conversion B (O)
GPIO11
EPWM6B
SCIRXDB
ECAP4		H3H2General-purpose input/output 11 (I/O/Z)
Enhanced PWM6 output B (O)
SCI-B receive data (I)
Enhanced CAP Input/Output 4 (I/O)
GPIO12
TZ1
CANTXB
MDXB		H2H3General-purpose input/output 12 (I/O/Z)
Trip Zone input 1 (I)
Enhanced CAN-B transmit (O)
McBSP-B transmit serial data (O)
GPIO13
TZ2
CANRXB
MDRB		H4J2General-purpose input/output 13 (I/O/Z)
Trip Zone input 2 (I)
Enhanced CAN-B receive (I)
McBSP-B receive serial data (I)
GPIO14H5J3General-purpose input/output 14 (I/O/Z)
TZ3/ XHOLDTrip Zone input 3/External Hold Request. XHOLD, when active (low), requests the external interface (XINTF) to release the external bus and place all buses and strobes into a high-impedance state. To prevent this from happening when TZ3 signal goes active, disable this function by writing XINTCNF2[HOLD] = 1. If this is not done, the XINTF bus will go into high impedance anytime TZ3 goes low. On the ePWM side, TZn signals are ignored by default, unless they are enabled by the code. The XINTF will release the bus when any current access is complete and there are no pending accesses on the XINTF. (I)
SCITXDB
MCLKXB		SCI-B Transmit (O)
McBSP-B transmit clock (I/O)
GPIO15K2K2General-purpose input/output 15 (I/O/Z)
TZ4/ XHOLDA Trip Zone input 4/External Hold Acknowledge. The pin function for this option is based on the direction chosen in the GPADIR register. If the pin is configured as an input, then TZ4 function is chosen. If the pin is configured as an output, then XHOLDA function is chosen. XHOLDA is driven active (low) when the XINTF has granted an XHOLD request. All XINTF buses and strobe signals will be in a high-impedance state. XHOLDA is released when the XHOLD signal is released. External devices should only drive the external bus when XHOLDA is active (low). (I/O)
SCIRXDB
MFSXB		SCI-B receive (I)
McBSP-B transmit frame synch (I/O)
GPIO16
SPISIMOA
CANTXB
TZ5		K4L1General-purpose input/output 16 (I/O/Z)
SPI slave in, master out (I/O)
Enhanced CAN-B transmit (O)
Trip Zone input 5 (I)
GPIO17
SPISOMIA
CANRXB
TZ6		J5L2General-purpose input/output 17 (I/O/Z)
SPI-A slave out, master in (I/O)
Enhanced CAN-B receive (I)
Trip zone input 6 (I)
GPIO18
SPICLKA
SCITXDB
CANRXA		L1M1General-purpose input/output 18 (I/O/Z)
SPI-A clock input/output (I/O)
SCI-B transmit (O)
Enhanced CAN-A receive (I)
GPIO19
SPISTEA
SCIRXDB
CANTXA		P3T4General-purpose input/output 19 (I/O/Z)
SPI-A slave transmit enable input/output (I/O)
SCI-B receive (I)
Enhanced CAN-A transmit (O)
GPIO20
EQEP1A
MDXA
CANTXB		L4R4General-purpose input/output 20 (I/O/Z)
Enhanced QEP1 input A (I)
McBSP-A transmit serial data (O)
Enhanced CAN-B transmit (O)
GPIO21
EQEP1B
MDRA
CANRXB		M4T5General-purpose input/output 21 (I/O/Z)
Enhanced QEP1 input B (I)
McBSP-A receive serial data (I)
Enhanced CAN-B receive (I)
GPIO22
EQEP1S
MCLKXA
SCITXDB		N4R5General-purpose input/output 22 (I/O/Z)
Enhanced QEP1 strobe (I/O)
McBSP-A transmit clock (I/O)
SCI-B transmit (O)
GPIO23
EQEP1I
MFSXA
SCIRXDB		P4P5General-purpose input/output 23 (I/O/Z)
Enhanced QEP1 index (I/O)
McBSP-A transmit frame synch (I/O)
SCI-B receive (I)
GPIO24
ECAP1
EQEP2A
MDXB		P5T6General-purpose input/output 24 (I/O/Z)
Enhanced capture 1 (I/O)
Enhanced QEP2 input A (I)
McBSP-B transmit serial data (O)
GPIO25
ECAP2
EQEP2B
MDRB		M5R6General-purpose input/output 25 (I/O/Z)
Enhanced capture 2 (I/O)
Enhanced QEP2 input B (I)
McBSP-B receive serial data (I)
GPIO26
ECAP3
EQEP2I
MCLKXB		K6P6General-purpose input/output 26 (I/O/Z)
Enhanced capture 3 (I/O)
Enhanced QEP2 index (I/O)
McBSP-B transmit clock (I/O)
GPIO27
ECAP4
EQEP2S
MFSXB		M6T7General-purpose input/output 27 (I/O/Z)
Enhanced capture 4 (I/O)
Enhanced QEP2 strobe (I/O)
McBSP-B transmit frame synch (I/O)
GPIO28
SCIRXDA
XZCS6		A12B13General-purpose input/output 28 (I/O/Z)
SCI receive data (I)
External Interface zone 6 chip select (O)
GPIO29
SCITXDA
XA19		C3D1General-purpose input/output 29. (I/O/Z)
SCI transmit data (O)
External Interface Address Line 19 (O)
GPIO30
CANRXA
XA18		C2C2General-purpose input/output 30 (I/O/Z)
Enhanced CAN-A receive (I)
External Interface Address Line 18 (O)
GPIO31
CANTXA
XA17		B2B3General-purpose input/output 31 (I/O/Z)
Enhanced CAN-A transmit (O)
External Interface Address Line 17 (O)
GPIO32
SDAA
EPWMSYNCI
ADCSOCAO		P6R7General-purpose input/output 32 (I/O/Z)
I2C data open-drain bidirectional port (I/OD)
Enhanced PWM external sync pulse input (I)
ADC start-of-conversion A (O)
GPIO33
SCLA
EPWMSYNCO
ADCSOCBO		N6P7General-purpose input/output 33 (I/O/Z)
I2C clock open-drain bidirectional port (I/OD)
Enhanced PWM external synch pulse output (O)
ADC start-of-conversion B (O)
GPIO34
ECAP1
XREADY		A13B14General-purpose input/output 34 (I/O/Z)
Enhanced Capture input/output 1 (I/O)
External Interface Ready signal
GPIO35
SCITXDA
XR/ W		B13C15General-purpose input/output 35 (I/O/Z)
SCI-A transmit data (O)
External Interface read, not write strobe
GPIO36
SCIRXDA
XZCS0		B12A13General-purpose input/output 36 (I/O/Z)
SCI-A receive data (I)
External Interface zone 0 chip select (O)
GPIO37
ECAP2
XZCS7		D11B12General-purpose input/output 37 (I/O/Z)
Enhanced Capture input/output 2 (I/O)
External Interface zone 7 chip select (O)
GPIO38
-
XWE0		C12E15General-purpose input/output 38 (I/O/Z)
-
External Interface Write Enable 0 (O). XWE0 defaults back to GPIO38 upon reset, during which time it will be high-impedance.
GPIO39
-
XA16		A2B4General-purpose input/output 39 (I/O/Z)
-
External Interface Address Line 16 (O)
GPIO40
-
XA0		E10C12General-purpose input/output 40 (I/O/Z)
-
External Interface Address Line 0
GPIO41
-
XA1		D10B11General-purpose input/output 41 (I/O/Z)
-
External Interface Address Line 1 (O)
GPIO42
-
XA2		B10C11General-purpose input/output 42 (I/O/Z)
-
External Interface Address Line 2 (O)
GPIO43
-
XA3		A10B10General-purpose input/output 43 (I/O/Z)
-
External Interface Address Line 3 (O)
GPIO44
-
XA4		A9C10General-purpose input/output 44 (I/O/Z)
-
External Interface Address Line 4 (O)
GPIO45
-
XA5		B9C9General-purpose input/output 45 (I/O/Z)
-
External Interface Address Line 5 (O)
GPIO46
-
XA6		E7B8General-purpose input/output 46 (I/O/Z)
-
External Interface Address Line 6 (O)
GPIO47
-
XA7		D6C8General-purpose input/output 47 (I/O/Z)
-
External Interface Address Line 7 (O)
GPIO48
ECAP5
XD31
SPISIMOD		M10R11General-purpose input/output 48 (I/O/Z)
Enhanced Capture input/output 5 (I/O)
External Interface Data Line 31 (O)
SPI-D slave in, master out (I/O)
GPIO49
ECAP6
XD30
SPISOMID		P10P11General-purpose input/output 49 (I/O/Z)
Enhanced Capture input/output 6 (I/O)
External Interface Data Line 30 (O)
SPI-D slave out, master in (I/O)
GPIO50
EQEP1A
XD29
SPICLKD		N10T12General-purpose input/output 50 (I/O/Z)
Enhanced QEP 1input A (I)
External Interface Data Line 29 (O)
SPI-D Clock input/output (I/O)
GPIO51
EQEP1B
XD28
SPISTED		N11R12General-purpose input/output 51 (I/O/Z)
Enhanced QEP 1input B (I)
External Interface Data Line 28 (O)
SPI-D slave transmit enable input/output (I/O)
GPIO52
EQEP1S
XD27		M11P12General-purpose input/output 52 (I/O/Z)
Enhanced QEP 1Strobe (I/O)
External Interface Data Line 27 (O)
GPIO53
EQEP1I
XD26		L11T13General-purpose input/output 53 (I/O/Z)
Enhanced QEP1 lndex (I/O)
External Interface Data Line 26 (O)
GPIO54
SPISIMOA
XD25
EQEP3A		P12R13General-purpose input/output 54 (I/O/Z)
SPI-A slave in, master out (I/O)
External Interface Data Line 25 (O)
Enhanced QEP3 input A (I)
GPIO55
SPISOMIA
XD24
EQEP3B		N12P13General-purpose input/output 55 (I/O/Z)
SPI-A slave out, master in (I/O)
External Interface Data Line 24 (O)
Enhanced QEP3 input B (I)
GPIO56
SPICLKA
XD23
EQEP3S		P13R14General-purpose input/output 56 (I/O/Z)
SPI-A clock (I/O)
External Interface Data Line 23 (O)
Enhanced QEP3 strobe (I/O)
GPIO57
SPISTEA
XD22
EQEP3I		N13P15General-purpose input/output 57 (I/O/Z)
SPI-A slave transmit enable (I/O)
External Interface Data Line 22 (O)
Enhanced QEP3 index (I/O)
GPIO58
MCLKRA
XD21
EPWM7A		P14N16General-purpose input/output 58 (I/O/Z)
McBSP-A receive clock (I/O)
External Interface Data Line 21 (O)
Enhanced PWM 7 output A and HRPWM channel (O)
GPIO59
MFSRA
XD20
EPWM7B		M13N15General-purpose input/output 59 (I/O/Z)
McBSP-A receive frame synch (I/O)
External Interface Data Line 20 (O)
Enhanced PWM 7 output B (O)
GPIO60
MCLKRB
XD19
EPWM8A		M14M16General-purpose input/output 60 (I/O/Z)
McBSP-B receive clock (I/O)
External Interface Data Line 19 (O)
Enhanced PWM 8 output A and HRPWM channel (O)
GPIO61
MFSRB
XD18
EPWM8B		L12M15General-purpose input/output 61 (I/O/Z)
McBSP-B receive frame synch (I/O)
External Interface Data Line 18 (O)
Enhanced PWM8 output B (O)
GPIO62
SCIRXDC
XD17
EPWM9A		L13M14General-purpose input/output 62 (I/O/Z)
SCI-C receive data (I)
External Interface Data Line 17 (O)
Enhanced PWM9 output A and HRPWM channel (O)
GPIO63
SCITXDC
XD16
EPWM9B		K13L16General-purpose input/output 63 (I/O/Z)
SCI-C transmit data (O)
External Interface Data Line 16 (O)
Enhanced PWM9 output B (O)
GPIO64
-
XD15		K12L15General-purpose input/output 64 (I/O/Z)
-
External Interface Data Line 15 (O)
GPIO65
-
XD14		K14L14General-purpose input/output 65 (I/O/Z)
-
External Interface Data Line 14 (O)
GPIO66
-
XD13		J11K15General-purpose input/output 66 (I/O/Z)
-
External Interface Data Line 13 (O)
GPIO67
-
XD12		J12K14General-purpose input/output 67 (I/O/Z)
-
External Interface Data Line 12 (O)
GPIO68
-
XD11		J13J15General-purpose input/output 68 (I/O/Z)
-
External Interface Data Line 11 (O)
GPIO69
-
XD10		H13J14General-purpose input/output 69 (I/O/Z)
-
External Interface Data Line 10 (O)
GPIO70
-
XD9		H12H16General-purpose input/output 70 (I/O/Z)
-
External Interface Data Line 9 (O)
GPIO71
-
XD8		G12H15General-purpose input/output 71 (I/O/Z)
-
External Interface Data Line 8 (O)
GPIO72
-
XD7		G13H14General-purpose input/output 72 (I/O/Z)
-
External Interface Data Line 7 (O)
GPIO73
-
XD6		F14G16General-purpose input/output 73 (I/O/Z)
-
External Interface Data Line 6 (O)
GPIO74
-
XD5		F13G15General-purpose input/output 74 (I/O/Z)
-
External Interface Data Line 5 (O)
GPIO75
-
XD4		F12G14General-purpose input/output 75 (I/O/Z)
-
External Interface Data Line 4 (O)
GPIO76
-
XD3		E13F16General-purpose input/output 76 (I/O/Z)
-
External Interface Data Line 3 (O)
GPIO77
-
XD2		E11F15General-purpose input/output 77 (I/O/Z)
-
External Interface Data Line 2 (O)
GPIO78
-
XD1		F10F14General-purpose input/output 78 (I/O/Z)
-
External Interface Data Line 1 (O)
GPIO79
-
XD0		C14E16General-purpose input/output 79 (I/O/Z)
-
External Interface Data Line 0 (O)
GPIO80
-
XA8		E6B7General-purpose input/output 80 (I/O/Z)
-
External Interface Address Line 8 (O)
GPIO81
-
XA9		C5C7General-purpose input/output 81 (I/O/Z)
-
External Interface Address Line 9 (O)
GPIO82
-
XA10		A5B6General-purpose input/output 82 (I/O/Z)
-
External Interface Address Line 10 (O)
GPIO83
-
XA11		B5C6General-purpose input/output 83 (I/O/Z)
-
External Interface Address Line 11 (O)
GPIO84
-
XA12		D5A5General-purpose input/output 84 (I/O/Z)
-
External Interface Address Line 12 (O)
GPIO85
-
XA13		D4B5General-purpose input/output 85 (I/O/Z)
-
External Interface Address Line 13 (O)
GPIO86
-
XA14		A3C5General-purpose input/output 86 (I/O/Z)
-
External Interface Address Line 14 (O)
GPIO87
-
XA15		B3A4General-purpose input/output 87 (I/O/Z)
-
External Interface Address Line 15 (O)
XRDA14D15External Interface Read Enable (O). The XRD pin is high-impedance on reset. It stays that way as long as the XINTF clock is turned off (which happens on reset).
XWE1C13E14External Memory Interface Write Enable for Upper 16-bits (O). The XWE1 pin is high-impedance on reset. It stays that way as long as the XINTF clock is turned off (which happens on reset).
CPU and I/O Power Pins
VDD18E8A6Oscillator and PLL Power Pin (1.8 V)
VDD18C7A11
VSSKB8A8Oscillator Kelvin Reference Ground. This pin should not be connected to Vss. See Figure 8-29 through Figure 8-31 for proper application board connections.
VDDD1C1CPU and logic digital power pins (1.1 V/1.2 V)
VDDE1C16
VDDG1E6
VDDK3E7
VDDM1E8
VDDN5E9
VDDP7E10
VDDJ3E11
VDDJ4F5
VDDK9F12
VDDL10G5
VDDN14G12
VDDK11H5
VDDH11H12
VDDH14J5
VDDG10J12
VDDE12K3
VDDD12K5
VDDC11K12
VDDC10L3
VDDB7L5
VDDC6L12
VDDE5M6
VDDC4M7
VDDM8
VDDM9
VDDM10
VDDM11
VDDP1
VDDP16
VDDIOD3A3Digital I/O power pins (3.3 V)
VDDIOF1A14
VDDIOJ1B9
VDDIOL2D5
VDDIOK5D6
VDDIOK7D8
VDDIOK8D11
VDDIOP11D12
VDDIOL14E4
VDDIOJ14E13Digital I/O power pins
VDDIOF11F4
VDDIOD14F13
VDDIOA11J1
VDDIOC9J4
VDDIOD7J13
VDDIOB6J16
VDDIOB4L4
VDDIOL13
VDDIOM4
VDDIOM13
VDDION5
VDDION6
VDDION8
VDDION11
VDDION12
VDDIOR9
VDDIOT3
VDDIOT14
VSSD2A1Digital ground pins
VSSF4A2
VSSG5A10
VSSH1A15
VSSJ2A16
VSSK1B1
VSSL3B2
VSSL5B15
VSSL7B16
VSSL8C3
VSSM9C4
VSSK10C13
VSSM12C14
VSSJ10D3
VSSH10D4
VSSG14D7
VSSG11D9
VSSE14D10
VSSD13D13
VSSB11D14
VSSE9E5
VSSD8E12
VSSA7F6
VSSA6F7
VSSA4F8
VSSF9
VSSF10
VSSF11Digital ground pins
VSSG4
VSSG6
VSSG7
VSSG8
VSSG9
VSSG10
VSSG11
VSSG13
VSSH4
VSSH6
VSSH7
VSSH8
VSSH9
VSSH10
VSSH11
VSSH13
VSSJ6
VSSJ7
VSSJ8
VSSJ9
VSSJ10
VSSJ11
VSSK1
VSSK4
VSSK6
VSSK7
VSSK8
VSSK9
VSSK10
VSSK11
VSSK13
VSSK16
VSSL6
VSSL7
VSSL8
VSSL9
VSSL10
VSSL11
VSSM5
VSSM12
VSSN4
VSSN7
VSSN9
VSSN10
VSSN13
VSSN14Digital ground pins
VSSP3
VSSP4
VSSP14
VSSR1
VSSR2
VSSR15
VSSR16
VSST1
VSST2
VSST15
VSST16
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