No special requirements are placed on the power up/down sequence of the various power pins to ensure the correct reset state for all the modules. However, if the 3.3-V transistors in the level shifting output buffers of the I/O pins are powered prior to the 1.1-V/1.2-V transistors, it is possible for the output buffers to turn on, causing a glitch to occur on the pin during power up. To avoid this behavior, power the V_DD pins prior to or simultaneously with the V_DDIO pins, ensuring that the V_DD pins have reached 0.7-V before the V_DDIO pins reach 0.7 V. The 1.8-V rail for the PLL and oscillator logic can be powered up along with V_DD/V_DDIO rails. The 1.8-V rail must be powered even if the PLL is not used. It should never be left unpowered. In any configuration, all the rails should ramp up within t_pup (5 ms, typical) to allow early stability of clocks and IOs.

There is a requirement on the XRS pin:

• During power up, the XRS pin must be held low for t_w(RSL1) after the input clock is stable. This is to enable the entire device to start from a known condition.

No voltage larger than a diode drop (0.7 V) above V_DDIO should be applied to any digital pin before powering up the device. Voltages applied to pins on an unpowered device can bias internal P-N junctions in unintended ways and produce unpredictable results.