ZHCSA18F March   2009  – February 2021 TMS320C28341 , TMS320C28342 , TMS320C28343 , TMS320C28343-Q1 , TMS320C28344 , TMS320C28345 , TMS320C28346 , TMS320C28346-Q1

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1. 3.1 Functional Block Diagram
  4. 4 Revision History
  5. 5 Device Comparison
    1. 5.1 Related Products
  6. 6 Terminal Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Signal Descriptions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings (1) (1)
    2. 7.2 ESD Ratings – Automotive
    3. 7.3 ESD Ratings – Commercial
    4. 7.4 Recommended Operating Conditions
    5. 7.5 Power Consumption Summary
      1. 7.5.1 TMS320C28346/C28344 (1) Current Consumption by Power-Supply Pins at 300-MHz SYSCLKOUT
      2. 7.5.2 TMS320C28345/C28343 (1) Current Consumption by Power-Supply Pins at 200-MHz SYSCLKOUT
      3. 7.5.3 Reducing Current Consumption
    6. 7.6 Electrical Characteristics
    7. 7.7 Thermal Resistance Characteristics
      1. 7.7.1 ZHH Package
      2. 7.7.2 ZFE Package
    8. 7.8 Thermal Design Considerations
    9. 7.9 Timing and Switching Characteristics
      1. 7.9.1 Timing Parameter Symbology
        1. 7.9.1.1 General Notes on Timing Parameters
        2. 7.9.1.2 Test Load Circuit
        3. 7.9.1.3 Device Clock Table
          1. 7.9.1.3.1 Clocking and Nomenclature (300-MHz Devices)
          2. 7.9.1.3.2 Clocking and Nomenclature (200-MHz Devices)
      2. 7.9.2 Power Sequencing
        1. 7.9.2.1 Power Management and Supervisory Circuit Solutions
        2. 7.9.2.2 Reset ( XRS) Timing Requirements
      3. 7.9.3 Clock Requirements and Characteristics
        1. 7.9.3.1 XCLKIN/X1 Timing Requirements – PLL Enabled
        2. 7.9.3.2 XCLKIN/X1 Timing Requirements – PLL Disabled
        3. 7.9.3.3 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled) (1) (1)
        4. 7.9.3.4 Timing Diagram
      4. 7.9.4 Peripherals
        1. 7.9.4.1 General-Purpose Input/Output (GPIO)
          1. 7.9.4.1.1 GPIO - Output Timing
            1. 7.9.4.1.1.1 General-Purpose Output Switching Characteristics
          2. 7.9.4.1.2 GPIO - Input Timing
            1. 7.9.4.1.2.1 General-Purpose Input Timing Requirements
          3. 7.9.4.1.3 Sampling Window Width for Input Signals
          4. 7.9.4.1.4 Low-Power Mode Wakeup Timing
            1. 7.9.4.1.4.1 IDLE Mode Timing Requirements (1)
            2. 7.9.4.1.4.2 IDLE Mode Switching Characteristics (1)
            3. 7.9.4.1.4.3 IDLE Mode Timing Diagram
            4. 7.9.4.1.4.4 STANDBY Mode Timing Requirements
            5. 7.9.4.1.4.5 STANDBY Mode Switching Characteristics
            6. 7.9.4.1.4.6 STANDBY Mode Timing Diagram
            7. 7.9.4.1.4.7 HALT Mode Timing Requirements
            8. 7.9.4.1.4.8 HALT Mode Switching Characteristics
            9. 7.9.4.1.4.9 HALT Mode Timing Diagram
        2. 7.9.4.2 Enhanced Control Peripherals
          1. 7.9.4.2.1 Enhanced Pulse Width Modulator (ePWM) Timing
            1. 7.9.4.2.1.1 ePWM Timing Requirements (1)
            2. 7.9.4.2.1.2 ePWM Switching Characteristics
          2. 7.9.4.2.2 Trip-Zone Input Timing
            1. 7.9.4.2.2.1 Trip-Zone Input Timing Requirements (1)
          3. 7.9.4.2.3 High-Resolution PWM Timing
            1. 7.9.4.2.3.1 High-Resolution PWM Characteristics at SYSCLKOUT = (150–300 MHz)
          4. 7.9.4.2.4 Enhanced Capture (eCAP) Timing
            1. 7.9.4.2.4.1 Enhanced Capture (eCAP) Timing Requirements (1)
            2. 7.9.4.2.4.2 eCAP Switching Characteristics
          5. 7.9.4.2.5 Enhanced Quadrature Encoder Pulse (eQEP) Timing
            1. 7.9.4.2.5.1 Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements (1)
            2. 7.9.4.2.5.2 eQEP Switching Characteristics
          6. 7.9.4.2.6 ADC Start-of-Conversion Timing
            1. 7.9.4.2.6.1 External ADC Start-of-Conversion Switching Characteristics
            2. 7.9.4.2.6.2 ADCSOCAO or ADCSOCBO Timing
        3. 7.9.4.3 External Interrupt Timing
          1. 7.9.4.3.1 External Interrupt Timing Requirements (1)
          2. 7.9.4.3.2 External Interrupt Switching Characteristics (1)
          3. 7.9.4.3.3 External Interrupt Timing Diagram
        4. 7.9.4.4 I2C Electrical Specification and Timing
          1. 7.9.4.4.1 I2C Timing
        5. 7.9.4.5 Serial Peripheral Interface (SPI) Timing
          1. 7.9.4.5.1 Master Mode Timing
            1. 7.9.4.5.1.1 SPI Master Mode External Timing (Clock Phase = 0) (1) (1) (1) (1) (1)
            2. 7.9.4.5.1.2 SPI Master Mode External Timing (Clock Phase = 1) (1) (1) (1) (1) (1)
          2. 7.9.4.5.2 Slave Mode Timing
            1. 7.9.4.5.2.1 SPI Slave Mode External Timing (Clock Phase = 0) (1) (1) (1) (1) (1)
            2. 7.9.4.5.2.2 SPI Slave Mode External Timing (Clock Phase = 1) (1) (1) (1) (1)
        6. 7.9.4.6 Multichannel Buffered Serial Port (McBSP) Timing
          1. 7.9.4.6.1 McBSP Transmit and Receive Timing
            1. 7.9.4.6.1.1 McBSP Timing Requirements (1) (1)
            2. 7.9.4.6.1.2 McBSP Switching Characteristics (1) (1)
          2. 7.9.4.6.2 McBSP as SPI Master or Slave Timing
            1. 7.9.4.6.2.1 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0) (1)
            2. 7.9.4.6.2.2 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)
            3. 7.9.4.6.2.3 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0) (1)
            4. 7.9.4.6.2.4 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)
            5. 7.9.4.6.2.5 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1) (1)
            6. 7.9.4.6.2.6 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)
            7. 7.9.4.6.2.7 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1) (1)
            8. 7.9.4.6.2.8 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1) (1)
      5. 7.9.5 Emulator Connection Without Signal Buffering for the MCU
      6. 7.9.6 External Interface (XINTF) Timing
        1. 7.9.6.1 USEREADY = 0
        2. 7.9.6.2 Synchronous Mode (USEREADY = 1, READYMODE = 0)
        3. 7.9.6.3 Asynchronous Mode (USEREADY = 1, READYMODE = 1)
        4. 7.9.6.4 XINTF Signal Alignment to XCLKOUT
        5. 7.9.6.5 External Interface Read Timing
          1. 7.9.6.5.1 External Interface Read Timing Requirements
          2. 7.9.6.5.2 External Interface Read Switching Characteristics
        6. 7.9.6.6 External Interface Write Timing
          1. 7.9.6.6.1 External Interface Write Switching Characteristics
        7. 7.9.6.7 External Interface Ready-on-Read Timing With One External Wait State
          1. 7.9.6.7.1 External Interface Read Switching Characteristics (Ready-on-Read, One Wait State)
          2. 7.9.6.7.2 External Interface Read Timing Requirements (Ready-on-Read, One Wait State)
          3. 7.9.6.7.3 Synchronous XREADY Timing Requirements (Ready-on-Read, One Wait State) (1)
          4. 7.9.6.7.4 Asynchronous XREADY Timing Requirements (Ready-on-Read, One Wait State)
        8. 7.9.6.8 External Interface Ready-on-Write Timing With One External Wait State
          1. 7.9.6.8.1 External Interface Write Switching Characteristics (Ready-on-Write, One Wait State)
          2. 7.9.6.8.2 Synchronous XREADY Timing Requirements (Ready-on-Write, One Wait State) Table 1-1
          3. 7.9.6.8.3 Asynchronous XREADY Timing Requirements (Ready-on-Write, One Wait State) (1)
        9. 7.9.6.9 XHOLD and XHOLDA Timing
          1. 7.9.6.9.1 XHOLD/ XHOLDA Timing Requirements (1) (1) (1)
  8. 8 Detailed Description
    1. 8.1 Brief Descriptions
      1. 8.1.1  C28x CPU
      2. 8.1.2  Memory Bus (Harvard Bus Architecture)
      3. 8.1.3  Peripheral Bus
      4. 8.1.4  Real-Time JTAG and Analysis
      5. 8.1.5  External Interface (XINTF)
      6. 8.1.6  M0, M1 SARAMs
      7. 8.1.7  L0, L1, L2, L3, L4, L5, L6, L7, H0, H1, H2, H3, H4, H5 SARAMs
      8. 8.1.8  Boot ROM
      9. 8.1.9  Security
      10. 8.1.10 Peripheral Interrupt Expansion (PIE) Block
      11. 8.1.11 External Interrupts (XINT1–XINT7, XNMI)
      12. 8.1.12 Oscillator and PLL
      13. 8.1.13 Watchdog
      14. 8.1.14 Peripheral Clocking
      15. 8.1.15 Low-Power Modes
      16. 8.1.16 Peripheral Frames 0, 1, 2, 3 (PFn)
      17. 8.1.17 General-Purpose Input/Output (GPIO) Multiplexer
      18. 8.1.18 32-Bit CPU-Timers (0, 1, 2)
      19. 8.1.19 Control Peripherals
      20. 8.1.20 Serial Port Peripherals
    2. 8.2 Peripherals
      1. 8.2.1  DMA Overview
      2. 8.2.2  32-Bit CPU-Timer 0, CPU-Timer 1, CPU-Timer 2
      3. 8.2.3  Enhanced PWM Modules
      4. 8.2.4  High-Resolution PWM (HRPWM)
      5. 8.2.5  Enhanced CAP Modules
      6. 8.2.6  Enhanced QEP Modules
      7. 8.2.7  External ADC Interface
      8. 8.2.8  Multichannel Buffered Serial Port (McBSP) Module
      9. 8.2.9  Enhanced Controller Area Network (eCAN) Modules (eCAN-A and eCAN-B)
      10. 8.2.10 Serial Communications Interface (SCI) Modules (SCI-A, SCI-B, SCI-C)
      11. 8.2.11 Serial Peripheral Interface (SPI) Module (SPI-A, SPI-D)
      12. 8.2.12 Inter-Integrated Circuit (I2C)
      13. 8.2.13 GPIO MUX
      14. 8.2.14 External Interface (XINTF)
    3. 8.3 Memory Maps
    4. 8.4 Register Map
      1. 8.4.1 Device Emulation Registers
    5. 8.5 Interrupts
      1. 8.5.1 External Interrupts
    6. 8.6 System Control
      1. 8.6.1 OSC and PLL Block
        1. 8.6.1.1 External Reference Oscillator Clock Option
        2. 8.6.1.2 PLL-Based Clock Module
        3. 8.6.1.3 Loss of Input Clock
      2. 8.6.2 Watchdog Block
    7. 8.7 Low-Power Modes Block
  9. 9 Applications, Implementation, and Layout
    1. 9.1 TI Design or Reference Design
  10. 10Device and Documentation Support
    1. 10.1 Getting Started
    2. 10.2 Device and Development Support Tool Nomenclature
    3. 10.3 Tools and Software
    4. 10.4 Documentation Support
    5. 10.5 支持资源
    6. 10.6 Trademarks
    7. 10.7 静电放电警告
    8. 10.8 术语表
  11. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

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8.2.13 GPIO MUX

On the 2834x devices, the GPIO MUX can multiplex up to three independent peripheral signals on a single GPIO pin in addition to providing individual pin bit-banging I/O capability. The GPIO MUX block diagram per pin is shown in Figure 8-16. Because of the open-drain capabilities of the I2C pins, the GPIO MUX block diagram for these pins differ. See the TMS320x2834x Delfino System Control and Interrupts Reference Guide for details.

Note:

There is a 2-SYSCLKOUT cycle delay from when the write to the GPxMUXn and GPxQSELn registers occurs to when the action is valid.

GUID-CA1489B6-ED5C-4E9C-8F8E-4D0B6D98ACAB-low.gif
x stands for the port, either A or B. For example, GPxDIR refers to either the GPADIR and GPBDIR register depending on the particular GPIO pin selected.
GPxDAT latch/read are accessed at the same memory location.
This is a generic GPIO MUX block diagram. Not all options may be applicable for all GPIO pins. See the TMS320x2834x Delfino System Control and Interrupts Reference Guide for pin-specific variations.
Figure 8-16 GPIO MUX Block Diagram

The device supports 88 GPIO pins. The GPIO control and data registers are mapped to Peripheral Frame 1 to enable 32-bit operations on the registers (along with 16-bit operations). Table 8-17 shows the GPIO register mapping.

Table 8-17 GPIO Registers
NAMEADDRESSSIZE (x16)DESCRIPTION
GPIO CONTROL REGISTERS (EALLOW PROTECTED)
GPACTRL0x6F802GPIO A Control Register (GPIO0 to 31)
GPAQSEL10x6F822GPIO A Qualifier Select 1 Register (GPIO0 to 15)
GPAQSEL20x6F842GPIO A Qualifier Select 2 Register (GPIO16 to 31)
GPAMUX10x6F862GPIO A MUX 1 Register (GPIO0 to 15)
GPAMUX20x6F882GPIO A MUX 2 Register (GPIO16 to 31)
GPADIR0x6F8A2GPIO A Direction Register (GPIO0 to 31)
GPAPUD0x6F8C2GPIO A Pullup Disable Register (GPIO0 to 31)
Reserved0x6F8E – 0x6F8F2
GPBCTRL0x6F902GPIO B Control Register (GPIO32 to 63)
GPBQSEL10x6F922GPIO B Qualifier Select 1 Register (GPIO32 to 47)
GPBQSEL20x6F942GPIOB Qualifier Select 2 Register (GPIO48 to 63)
GPBMUX10x6F962GPIO B MUX 1 Register (GPIO32 to 47)
GPBMUX20x6F982GPIO B MUX 2 Register (GPIO48 to 63)
GPBDIR0x6F9A2GPIO B Direction Register (GPIO32 to 63)
GPBPUD0x6F9C2GPIO B Pullup Disable Register (GPIO32 to 63)
Reserved0x6F9E – 0x6FA58
GPCMUX10x6FA62GPIO C MUX1 Register (GPIO64 to 79)
GPCMUX20x6FA82GPIO C MUX2 Register (GPIO80 to 87)
GPCDIR0x6FAA2GPIO C Direction Register (GPIO64 to 87)
GPCPUD0x6FAC2GPIO C Pullup Disable Register (GPIO64 to 87)
Reserved0x6FAE – 0x6FBF18
GPIO DATA REGISTERS (NOT EALLOW PROTECTED)
GPADAT0x6FC02GPIO A Data Register (GPIO0 to 31)
GPASET0x6FC22GPIO A Data Set Register (GPIO0 to 31)
GPACLEAR0x6FC42GPIO A Data Clear Register (GPIO0 to 31)
GPATOGGLE0x6FC62GPIO A Data Toggle Register (GPIO0 to 31)
GPBDAT0x6FC82GPIO B Data Register (GPIO32 to 63)
GPBSET0x6FCA2GPIO B Data Set Register (GPIO32 to 63)
GPBCLEAR0x6FCC2GPIO B Data Clear Register (GPIO32 to 63)
GPBTOGGLE0x6FCE2GPIOB Data Toggle Register (GPIO32 to 63)
GPCDAT0x6FD02GPIO C Data Register (GPIO64 to 87)
GPCSET0x6FD22GPIO C Data Set Register (GPIO64 to 87)
GPCCLEAR0x6FD42GPIO C Data Clear Register (GPIO64 to 87)
GPCTOGGLE0x6FD62GPIO C Data Toggle Register (GPIO64 to 87)
Reserved0x6FD8 – 0x6FDF8
GPIO INTERRUPT AND LOW-POWER MODES SELECT REGISTERS (EALLOW PROTECTED)
GPIOXINT1SEL0x6FE01XINT1 GPIO Input Select Register (GPIO0 to 31)
GPIOXINT2SEL0x6FE11XINT2 GPIO Input Select Register (GPIO0 to 31)
GPIOXNMISEL0x6FE21XNMI GPIO Input Select Register (GPIO0 to 31)
GPIOXINT3SEL0x6FE31XINT3 GPIO Input Select Register (GPIO32 to 63)
GPIOXINT4SEL0x6FE41XINT4 GPIO Input Select Register (GPIO32 to 63)
GPIOXINT5SEL0x6FE51XINT5 GPIO Input Select Register (GPIO32 to 63)
GPIOXINT6SEL0x6FE61XINT6 GPIO Input Select Register (GPIO32 to 63)
GPIOINT7SEL0x6FE71XINT7 GPIO Input Select Register (GPIO32 to 63)
GPIOLPMSEL0x6FE82LPM GPIO Select Register (GPIO0 to 31)
Reserved0x6FEA – 0x6FFF22
Table 8-18 GPIO-A Mux Peripheral Selection Matrix
REGISTER BITSPERIPHERAL SELECTION
GPADIR
GPADAT
GPASET
GPACLR
GPATOGGLE		GPAMUX1
GPAQSEL1		GPIOx
GPAMUX1 = 0,0		PER1
GPAMUX1 = 0, 1		PER2
GPAMUX1 = 1, 0		PER3
GPAMUX1 = 1, 1
QUALPRD001, 0GPIO0 (I/O)EPWM1A (O)ReservedReserved
13, 2GPIO1 (I/O)EPWM1B (O)ECAP6 (I/O)MFSRB (I/O)
25, 4GPIO2 (I/O)EPWM2A (O)ReservedReserved
37, 6GPIO3 (I/O)EPWM2B (O)ECAP5 (I/O)MCLKRB (I/O)
49, 8GPIO4 (I/O)EPWM3A (O)ReservedReserved
511, 10GPIO5 (I/O)EPWM3B (O)MFSRA (I/O)ECAP1 (I/O)
613, 12GPIO6 (I/O)EPWM4A (O)EPWMSYNCI (I)EPWMSYNCO (O)
715, 14GPIO7 (I/O)EPWM4B (O)MCLKRA (I/O)ECAP2 (I/O)
QUALPRD1817, 16GPIO8 (I/O)EPWM5A (O)CANTXB (O)ADCSOCAO (O)
919, 18GPIO9 (I/O)EPWM5B (O)SCITXDB (O)ECAP3 (I/O)
1021, 20GPIO10 (I/O)EPWM6A (O)CANRXB (I)ADCSOCBO (O)
1123, 22GPIO11 (I/O)EPWM6B (O)SCIRXDB (I)ECAP4 (I/O)
1225, 24GPIO12 (I/O)TZ1 (I)CANTXB (O)MDXB (O)
1327, 26GPIO13 (I/O)TZ2 (I)CANRXB (I)MDRB (I)
1429, 28GPIO14 (I/O)TZ3 (I)/ XHOLD (I)SCITXDB (O)MCLKXB (I/O)
1531, 30GPIO15 (I/O)TZ4 (I)/ XHOLDA (O)SCIRXDB (I)MFSXB (I/O)
GPAMUX2
GPAQSEL2		GPAMUX2 = 0, 0GPAMUX2 = 0, 1GPAMUX2 = 1, 0GPAMUX2 = 1, 1
QUALPRD2161, 0GPIO16 (I/O)SPISIMOA (I/O)CANTXB (O)TZ5 (I)
173, 2GPIO17 (I/O)SPISOMIA (I/O)CANRXB (I)TZ6 (I)
185, 4GPIO18 (I/O)SPICLKA (I/O)SCITXDB (O)CANRXA (I)
197, 6GPIO19 (I/O)SPISTEA (I/O)SCIRXDB (I)CANTXA (O)
209, 8GPIO20 (I/O)EQEP1A (I)MDXA (O)CANTXB (O)
2111, 10GPIO21 (I/O)EQEP1B (I)MDRA (I)CANRXB (I)
2213, 12GPIO22 (I/O)EQEP1S (I/O)MCLKXA (I/O)SCITXDB (O)
2315, 14GPIO23 (I/O)EQEP1I (I/O)MFSXA (I/O)SCIRXDB (I)
QUALPRD32417, 16GPIO24 (I/O)ECAP1 (I/O)EQEP2A (I)MDXB (O)
2519, 18GPIO25 (I/O)ECAP2 (I/O)EQEP2B (I)MDRB (I)
2621, 20GPIO26 (I/O)ECAP3 (I/O)EQEP2I (I/O)MCLKXB (I/O)
2723, 22GPIO27 (I/O)ECAP4 (I/O)EQEP2S (I/O)MFSXB (I/O)
2825, 24GPIO28 (I/O)SCIRXDA (I)XZCS6 (O)
2927, 26GPIO29 (I/O)SCITXDA (O)XA19 (O)
3029, 28GPIO30 (I/O)CANRXA (I)XA18 (O)
3131, 30GPIO31 (I/O)CANTXA (O)XA17 (O)
Table 8-19 GPIO-B Mux Peripheral Selection Matrix
REGISTER BITSPERIPHERAL SELECTION
GPBDIR
GPBDAT
GPBSET
GPBCLR
GPBTOGGLE		GPBMUX1
GPBQSEL1		GPIOx
GPBMUX1 = 0, 0		PER1
GPBMUX1 = 0, 1		PER2
GPBMUX1 = 1, 0		PER3
GPBMUX1 = 1, 1
QUALPRD001, 0GPIO32 (I/O)SDAA (I/OC)(1)EPWMSYNCI (I)ADCSOCAO (O)
13, 2GPIO33 (I/O)SCLA (I/OC)(1)EPWMSYNCO (O)ADCSOCBO (O)
25, 4GPIO34 (I/O)ECAP1 (I/O)XREADY (I)
37, 6GPIO35 (I/O)SCITXDA (O)XR/ W (O)
49, 8GPIO36 (I/O)SCIRXDA (I)XZCS0 (O)
511, 10GPIO37 (I/O)ECAP2 (I/O)XZCS7 (O)
613, 12GPIO38 (I/O)ReservedXWE0 (O)
715, 14GPIO39 (I/O)XA16 (O)
QUALPRD1817, 16GPIO40 (I/O)XA0 (O)
919, 18GPIO41 (I/O)XA1 (O)
1021, 20GPIO42 (I/O)XA2 (O)
1123, 22GPIO43 (I/O)XA3 (O)
1225, 24GPIO44 (I/O)XA4 (O)
1327, 26GPIO45 (I/O)XA5 (O)
1429, 28GPIO46 (I/O)XA6 (O)
1531, 30GPIO47 (I/O)XA7 (O)
GPBMUX2
GPBQSEL2		GPBMUX2 = 0, 0GPBMUX2 = 0, 1GPBMUX2 = 1, 0GPBMUX2 = 1, 1
QUALPRD2161, 0GPIO48 (I/O)ECAP5 (I/O)XD31 (I/O)SPISIMOD (I/O)
173, 2GPIO49 (I/O)ECAP6 (I/O)XD30 (I/O)SPISOMID (I/O)
185, 4GPIO50 (I/O)EQEP1A (I)XD29 (I/O)SPICLKD (I/O)
197, 6GPIO51 (I/O)EQEP1B (I)XD28 (I/O)SPISTED (I/O)
209, 8GPIO52 (I/O)EQEP1S (I/O)XD27 (I/O)Reserved
2111, 10GPIO53 (I/O)EQEP1I (I/O)XD26 (I/O)Reserved
2213, 12GPIO54 (I/O)SPISIMOA (I/O)XD25 (I/O)EQEP3A (I)
2315, 14GPIO55 (I/O)SPISOMIA (I/O)XD24 (I/O)EQEP3B (I)
QUALPRD32417, 16GPIO56 (I/O)SPICLKA (I/O)XD23 (I/O)EQEP3S (I/O)
2519, 18GPIO57 (I/O)SPISTEA (I/O)XD22 (I/O)EQEP3I (I/O)
2621, 20GPIO58 (I/O)MCLKRA (I/O)XD21 (I/O)EPWM7A (O)
2723, 22GPIO59 (I/O)MFSRA (I/O)XD20 (I/O)EPWM7B (O)
2825, 24GPIO60 (I/O)MCLKRB (I/O)XD19 (I/O)EPWM8A (O)
2927, 26GPIO61 (I/O)MFSRB (I/O)XD18 (I/O)EPWM8B (O)
3029, 28GPIO62 (I/O)SCIRXDC (I)XD17 (I/O)EPWM9A (O)
3131, 30GPIO63 (I/O)SCITXDC (O)XD16 (I/O)EPWM9B (O)
(1) Open drain
Table 8-20 GPIO-C Mux Peripheral Selection Matrix
REGISTER BITSPERIPHERAL SELECTION
GPCDIR
GPCDAT
GPCSET
GPCCLR
GPCTOGGLE		GPCMUX1GPIOx or PER1
GPCMUX1 = 0, 0 or 0, 1		PER2 or PER3
GPCMUX1 = 1, 0 or 1, 1
no qual01, 0GPIO64 (I/O)XD15 (I/O)
13, 2GPIO65 (I/O)XD14 (I/O)
25, 4GPIO66 (I/O)XD13 (I/O)
37, 6GPIO67 (I/O)XD12 (I/O)
49, 8GPIO68 (I/O)XD11 (I/O)
511, 10GPIO69 (I/O)XD10 (I/O)
613, 12GPIO70 (I/O)XD9 (I/O)
715, 14GPIO71 (I/O)XD8 (I/O)
no qual817, 16GPIO72 (I/O)XD7 (I/O)
919, 18GPIO73 (I/O)XD6 (I/O)
1021, 20GPIO74 (I/O)XD5 (I/O)
1123, 22GPIO75 (I/O)XD4 (I/O)
1225, 24GPIO76 (I/O)XD3 (I/O)
1327, 26GPIO77 (I/O)XD2 (I/O)
1429, 28GPIO78 (I/O)XD1 (I/O)
1531, 30GPIO79 (I/O)XD0 (I/O)
GPCMUX2GPCMUX2 = 0, 0 or 0, 1GPCMUX2 = 1, 0 or 1, 1
no qual161, 0GPIO80 (I/O)XA8 (O)
173, 2GPIO81 (I/O)XA9 (O)
185, 4GPIO82 (I/O)XA10 (O)
197, 6GPIO83 (I/O)XA11 (O)
209, 8GPIO84 (I/O)XA12 (O)
2111, 10GPIO85 (I/O)XA13 (O)
2213, 12GPIO86 (I/O)XA14 (O)
2315, 14GPIO87 (I/O)XA15 (O)

The user can select the type of input qualification for each GPIO pin through the GPxQSEL1/2 registers from four choices:

  • Synchronization To SYSCLKOUT Only (GPxQSEL1/2 = 0, 0): This is the default mode of all GPIO pins at reset and it simply synchronizes the input signal to the system clock (SYSCLKOUT).
  • Qualification Using Sampling Window (GPxQSEL1/2 = 0, 1 and 1, 0): In this mode the input signal, after synchronization to the system clock (SYSCLKOUT), is qualified by a specified number of cycles before the input is allowed to change.
    GUID-97587CB1-7282-4DD8-9502-0786E1A20B66-low.gifFigure 8-17 Qualification Using Sampling Window
  • The sampling period is specified by the QUALPRD bits in the GPxCTRL register and is configurable in groups of 8 signals. It specifies a multiple of SYSCLKOUT cycles for sampling the input signal. The sampling window is either 3-samples or 6-samples wide and the output is only changed when all samples are the same (all 0s or all 1s) as shown in Figure 8-17 (for 6-sample mode).
  • No Synchronization (GPxQSEL1/2 = 1,1): This mode is used for peripherals where synchronization is not required (synchronization is performed within the peripheral).

Due to the multilevel multiplexing that is required on the device, there may be cases where a peripheral input signal can be mapped to more then one GPIO pin. Also, when an input signal is not selected, the input signal will default to either a 0 or 1 state, depending on the peripheral.
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