The devices have an on-chip, PLL-based clock module. This module provides all the necessary clocking signals for the device, as well as control for low-power mode entry. The PLL has a 5-bit ratio control PLLCR[DIV] to select different CPU clock rates. The watchdog module should be disabled before writing to the PLLCR register. It can be re-enabled (if need be) after the PLL module has stabilized. The input clock and PLLCR[DIV] bits should be chosen in such a way that the output frequency of the PLL (VCOCLK) falls between 400 MHz and 600 MHz. The PLLSTS[DIVSEL] bit should be selected such that SYSCLKOUT(CLKIN) does not exceed the maximum operating frequency allowed for the device (300 MHz or 200 MHz). For example, suppose it is desired to operate a 300-MHz device at 100 MHz using a 20-MHz OSCCLK input (that is, for power savings). The PLL should be configured for OSCCLK * 20, which produces VCOCLK = 400 MHz. PLLSTS[DIVSEL] should then be configured for /4 mode, resulting in the desired 100-MHz CLKIN to the CPU. The PLL should not be configured for OSCCLK * 10 with PLLSTS[DIVSEL] set for /2 mode. This combination would produce VCOCLK = 200 MHz, which does not fall within the required 400 MHz to 600 MHz range.

The PLL-based clock module provides two modes of operation:

• Crystal-operation - This mode allows the use of an external crystal/resonator to provide the time base to the device.
• External clock source operation - This mode allows the internal oscillator to be bypassed. The device clocks are generated from an external clock source input on the X1 or the XCLKIN pin.