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ZHCS277C August 2011 – April 2014 TMS320C5532 , TMS320C5533 , TMS320C5534 , TMS320C5535

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机械数据 (封装 | 引脚)

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5 Specifications

For the device maximum operating frequency, see Section 7.1.2, Device Nomenclature.

5.1 Absolute Maximum Ratings

Over Operating Case Temperature Range (Unless Otherwise Noted)⁽¹⁾

Supply voltage ranges:	Digital Core (CV_DD, CV_DDRTC, USB_V_DD1P3)⁽²⁾	–0.5 V to 1.7 V
	I/O, 1.8 V, 2.5 V, 2.75 V, 3.3 V (DV_DDIO, DV_DDRTC) 3.3 V USB supplies USB PHY (USB_V_DDOSC, USB_V_DDPLL, USB_V_DDA3P3)⁽²⁾	–0.5 V to 4.2 V
	LDOI	–0.5 V to 4.2 V
	Analog, 1.3 V (V_{DDA_PLL}, USB_V_DDA1P3, V_{DDA_ANA})⁽²⁾	–0.5 V to 1.7 V
Input and Output voltage ranges:	V_I I/O, All pins with DV_DDIO or USB_V_DDOSC or USB_V_DDPLL or USB_V_DDA3P3 as supply source	–0.5 V to 4.2 V
	V_O I/O, All pins with DV_DDIO or USB_V_DDOSC or USB_V_DDPLLor USB_V_DDA3P3 as supply source	–0.5 V to 4.2 V
	RTC_XI and RTC_XO	–0.5 V to 1.7 V
	V_I and V_O, GPAIN[0]	–0.5 V to 4.2 V
	V_I and V_O, GPAIN[3:1]	–0.5 V to 1.7 V
	V_O, BG_CAP	–0.5 V to 1.7 V
	USB_V_BUS Input	-0.5 V to 5.5 V
	ANA_LDOO, DSP_LDOO, and USB_LDOO⁽³⁾	–0.5 V to 1.7 V
Operating case temperature ranges, T_c:	Commercial Temperature (default)	-10°C to 70°C

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to V_SS.

(3) DSP_LDOO on TMS320C5533 and C5532 and USB_LDOO on TMS320C5532 are not supported and must be left unconnected.

(4) Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by electrostatic discharges into the device.

(5) Level listed is the passing level per ANSI/ESDA/JEDEC JS-001. JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process, and manufacturing with less than 500 V HBM is possible if necessary precautions are taken. Pins listed as 1000 V may actually have higher performance.

(6) Level listed is the passing level per EIA-JEDEC JESD22-C101E. JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process. Pins listed as 250 V may actually have higher performance.

5.2 Recommended Operating Conditions

				MIN	NOM	MAX	UNIT
	CV_DD	Supply voltage, Digital Core	50 MHz	0.998	1.05	1.15	V
			100 MHz	1.24	1.3	1.43	V
Core Supplies	CV_DDRTC	Supply voltage, RTC and RTC OSC	32.768 kHz	0.998		1.43	V
	USB_V_DD1P3	Supply voltage, Digital USB		1.24	1.3	1.43	V
	USB_V_DDA1P3	Supply voltage, 1.3 V Analog USB		1.24	1.3	1.43	V
	V_{DDA_ANA}	Supply voltage, 1.3 V SAR and Pwr Mgmt		1.24	1.3	1.43	V
	V_{DDA_PLL}	Supply voltage, System PLL		1.24	1.3	1.43	V
	USB_V_DDPLL	Supply voltage, 3.3 V USB PLL		2.97	3.3	3.63	V
I/O Supplies	DV_DDIO DV_DDRTC	Supply voltage, I/O, 3.3 V		2.97	3.3	3.63	V
		Supply voltage, I/O, 2.75 V		2.48	2.75	3.02	V
		Supply voltage, I/O, 2.5 V		2.25	2.5	2.75	V
		Supply voltage, I/O, 1.8 V		1.65	1.8	1.98	V
	USB_V_DDOSC	Supply voltage, I/O, 3.3 V USB OSC		2.97	3.3	3.63	V
	USB_V_DDA3P3	Supply voltage, I/O, 3.3 V Analog USB PHY		2.97	3.3	3.63	V
	LDOI	Supply voltage, Analog Pwr Mgmt and LDO Inputs		1.8		3.6	V
	V_SS	Supply ground, Digital I/O
	V_SSRTC	Supply ground, RTC
	USB_V_SSOSC	Supply ground, USB OSC
	USB_V_SSPLL	Supply ground, USB PLL
GND	USB_V_SSA3P3	Supply ground, 3.3 V Analog USB PHY		0	0	0	V
	USB_V_SSA1P3	Supply ground, USB 1.3 V Analog USB PHY
	USB_V_SSREF	Supply ground, USB Reference Current
	V_{SSA_PLL}	Supply ground, System PLL
	USB_V_SS1P3	Supply ground, 1.3 V Digital USB PHY
	V_{SSA_ANA}	Supply ground, SAR and Pwr Mgmt
V_IH⁽¹⁾		High-level input voltage, 3.3, 2.75, 2.5, 1.8 V I/O (except GPAIN[3:0 ] pins)⁽²⁾		0.7 * DV_DD		DV_DD + 0.3	V
V_IL⁽¹⁾		Low-level input voltage, 3.3, 2.75, 2.5, 1.8 V I/O (except GPAIN[3:0 ] pins)⁽²⁾		-0.3		0.3 * DV_DD	V
		Input voltage, GPAIN0 pin⁽³⁾		-0.3		3.6	V
V_IN		Input voltage, GPAIN[3:1] pins		-0.3		V_{DDA_ANA} + 0.3	V
T_c		Operating case temperature	Default (Commercial)	-10		70	°C
F_SYSCLK		DSP Operating Frequency (SYSCLK)	1.05 V	0		50	MHz
			1.3 V	0		100	MHz

(1) DV_DD refers to the pin I/O supply voltage. To determine the I/O supply voltage for each pin, see Section 4.2, Signal Descriptions.

(2) The I2C pin SDA and SCL do not feature fail-safe I/O buffers. These pin could potentially draw current when the DV_DDIO is powered down. Due to the fact that different voltage devices can be connected to I2C bus and the I2C inputs are LVCMOS, the level of logic 0 (low) and logic 1 (high) are not fixed and depend on DV_DDIO.

(3) The GNDON bit in the SARPINCTRL register must be set to "1" before SAR channels 0, 1, or 2 are enabled via the CHSEL bit in the SARCTRL register, when V_IN greater than V_{DDA_ANA}.

5.3 Electrical Characteristics

Over Recommended Ranges of Supply Voltage and Operating Temperature (Unless Otherwise Noted)

PARAMETER		TEST CONDITIONS ⁽¹⁾		MIN	TYP	MAX	UNIT
	Full speed: USB_DN and USB_DP⁽⁷⁾			2.8		USB_V_DDA3P3	V
	High speed: USB_DN and USB_DP⁽⁷⁾			360		440	mV
V_OH	High-level output voltage, 3.3, 2.75, 2.5, 1.8 V I/O (except GPAIN[3:0 ] pins)	IO = I_OH		0.8 * DV_DD			V
	High-level output voltage, GPAIN[3:1] pins	IO = I_OH		0.8 * V_{DDA_ANA}			V
	Full speed: USB_DN and USB_DP⁽⁷⁾			0.0		0.3	V
	High speed: USB_DN and USB_DP⁽⁷⁾			–10		10	mV
V_OL	Low-level output voltage, 3.3, 2.75, 2.5, 1.8V I/O (except I2C and GPAIN[3:0 ] pins)	IO = I_OL				0.2 * DV_DD	V
	Low-level output voltage, I2C pins⁽³⁾	V_DD> 2 V, I_O_L= 3 mA		0		0.4	V
	Low-level output voltage, GPAIN[3:0 ] pins	IO = I_OL				0.2 * V_{DDA_ANA}	V
V_HYS	Input hysteresis⁽²⁾	DV_DD= 3.3 V			162		mV
V_HYS	Input hysteresis⁽²⁾	DV_DD= 2.5 V			141		mV
		DV_DD= 1.8 V			122		mV
	USB_LDOO voltage			1.24	1.3	1.43	V
	ANA_LDOO voltage			1.24	1.3	1.43	V
V_LDO	DSP_LDOO voltage	DSP_LDO_V bit in the LDOCNTL register = 1		1.24	1.3	1.43	V
	DSP_LDOO voltage	DSP_LDO_V bit in the LDOCNTL register = 0		0.998	1.05	1.15	V
I_SD	DSP_LDO shutdown current⁽⁶⁾	LDOI = V_MIN		250			mA
I_SD	ANA_LDO shutdown current⁽⁶⁾	LDOI = V_MIN		4			mA
	USB_LDO shutdown current⁽⁶⁾	LDOI = V_MIN		25			mA
I_ILPU⁽⁸⁾⁽¹⁰⁾	Input current [DC] (except WAKEUP, I2C and GPAIN[3:0 ] pins)	Input only pin, internal pulldown or pullup disabled		-5		+5	μA
		DV_DD = 3.3 V with internal pullup enabled⁽⁴⁾			-59 to -161		μA
		DV_DD = 2.5 V with internal pullup enabled⁽⁴⁾			-31 to -93		μA
		DV_DD = 1.8 V with internal pullup enabled⁽⁴⁾			-14 to -44		μA
I_IHPD⁽⁸⁾⁽¹⁰⁾	Input current [DC] (except WAKEUP, I2C and GPAIN[3:0 ] pins)	Input only pin, internal pulldown or pullup disabled		-5		+5	μA
		DV_DD = 3.3 V with internal pulldown enabled⁽⁴⁾			52 to 158		μA
		DV_DD = 2.5 V with internal pulldown enabled⁽⁴⁾			27 to 83		μA
		DV_DD = 1.8 V with internal pulldown enabled⁽⁴⁾			11 to 35		μA
I_IH/ I_IL⁽¹⁰⁾	Input current [DC], ALL pins	V_I = V_SS to DV_DD with internal pullups and pulldowns disabled.		-5		+5	μA
I_OH⁽¹⁰⁾	High-level output current [DC]	All Pins (except USB, CLKOUT, and GPAIN[3:0 ] pins)		-4			mA
		CLKOUT pin	DV_DD = 3.3 V	-6			mA
		CLKOUT pin	DV_DD = 1.8 V	-4			mA
		GPAIN[3:1] pins (GPAIN0 is open-drain and cannot drive high)	DV_DD = V_{DDA_ANA}= 1.3 V, External Regulator⁽⁵⁾	-4			mA
			DV_DD = V_{DDA_ANA}= 1.3 V, Internal Regulator⁽⁵⁾	-100			μA
I_OL⁽¹⁰⁾	Low-level output current [DC]	All Pins (except USB, CLKOUT, and GPAIN[3:0 ])				+4	mA
		CLKOUT pin	DV_DD = 3.3 V			+6	mA
		CLKOUT pin	DV_DD = 1.8 V			+4	mA
			DV_DD = V_{DDA_ANA}= 1.3 V, external regulator			+4	mA
		GPAIN[3:0 ]	DV_DD = V_{DDA_ANA}= 1.3 V, internal regulator⁽⁵⁾			+4	mA
I_OZ⁽⁹⁾	I/O Off-state output current	All Pins (except USB and GPAIN[3:0 ])		-10		+10	μA
		GPAIN[3:0 ] pins		-10		+10	μA
I_OLBH⁽¹¹⁾	Bus Holder pull low current when CV_DD is powered "OFF"	Supply voltage, I/O, 3.3 V				2.2	mA
		Supply voltage, I/O, 2.75 V				1.6	mA
		Supply voltage, I/O, 2.5 V				1.4	mA
		Supply voltage, I/O, 1.8 V				0.72	mA
I_OHBH⁽¹¹⁾	Bus Holder pull high current when CV_DD is powered "OFF"	Supply voltage, I/O, 3.3 V		-1.3			mA
		Supply voltage, I/O, 2.75 V		-0.97			mA
		Supply voltage, I/O, 2.5 V		-0.83			mA
		Supply voltage, I/O, 1.8 V		-0.46			mA
P	Core (CV_DD) supply power	Active, CV_DD= 1.3 V, DSP clock = 100 MHz, Clock source = RTC on-chip Oscillator Room Temp (25 °C), 75% DMAC + 25% ADD (typical sine wave data switching)			0.22		mW/MHz
		Active, CV_DD= 1.05 V, DSP clock = 50 MHz, Clock source = RTC on-chip Oscillator Room Temp (25 °C), 75% DMAC + 25% ADD (typical data switching)			0.15		mW/MHz
		Active, CV_DD= 1.3 V, DSP clock = 100 MHz, Clock source = RTC on-chip Oscillator Room Temp (25 °C), 75% DMAC + 25% NOP (typical sine wave data switching)			0.22		mW/MHz
		Active, CV_DD= 1.05 V, DSP clock = 50 MHz, Clock source = RTC on-chip Oscillator Room Temp (25 °C), 75% DMAC + 25% NOP (typical data switching)			0.14		mW/MHz
		Standby, CV_DD= 1.3 V, Master clock disabled, Clock source = RTC on-chip Oscillator Room Temp (25 °C), DARAM and SARAM in active mode			0.44		mW
		Standby, CV_DD= 1.05 V, Master clock disabled, Clock source = RTC on-chip Oscillator Room Temp (25 °C), DARAM and SARAM in active mode			0.26		mW
		Standby, CV_DD= 1.3 V, Master clock disabled, Clock source = RTC on-chip Oscillator Room Temp (25 °C), DARAM in retention and SARAM in active mode			0.40		mW
		Standby, CV_DD= 1.05 V, Master clock disabled, Clock source = RTC on-chip Oscillator Room Temp (25 °C), DARAM in retention and SARAM in active mode			0.23		mW
		Standby, CV_DD= 1.3 V, Master clock disabled, Clock source = RTC on-chip Oscillator Room Temp (25 °C), DARAM in active mode and SARAM in retention			0.28		mW
		Standby, CV_DD= 1.05 V, Master clock disabled, Clock source = RTC on-chip Oscillator Room Temp (25 °C), DARAM in active mode and SARAM in retention			0.15		mW
I	Analog PLL (V_{DDA_PLL}) supply current	V_{DDA_PLL}= 1.3 V Room Temp (25 °C), Phase detector = 170 kHz, VCO = 100 MHz			0.7		mA
	SAR Analog (V_{DDA_ANA}) supply current	V_{DDA_ANA}= 1.3 V, SAR clock = 2 MHz, Temp (70 °C)				1	mA
C_I	Input capacitance					4	pF
C_o	Output capacitance					4	pF

(1) For test conditions shown as MIN, MAX, or TYP, use the appropriate value specified in the recommended operating conditions table.

(2) Applies to all input pins except WAKEUP, I2C pins, GPAIN[3:0 ], RTC_XI, and USB_MXI.

(3) V_DD is the voltage to which the I2C bus pullup resistors are connected.

(4) Applies only to pins with an internal pullup (IPU) or pulldown (IPD) resistor.

(5) When the ANA_LDO supplies V_{DDA_ANA}, it is not recommended to use the GPAIN[3:1] signals for general-purpose outputs (driving high). The I_SD parameter of the ANA_LDO is too low to drive any realistic load on the GPAIN[3:1] pins while also supplying the PLL through V_{DDA_PLL} and the SAR through V_{DDA_ANA}.

(6) I_SD is the amount of current the LDO is ensured to deliver before shutting down to protect itself.

(7) The USB I/Os adhere to the Universal Bus Specification Revision 2.0 (USB2.0 spec).

(8) I_I applies to input-only pins and bi-directional pins. For input-only pins, I_I indicates the input leakage current. For bi-directional pins, I_I indicates the input leakage current and off-state (Hi-Z) output leakage current.

(9) I_OZ applies to output-only pins, indicating off-state (Hi-Z) output leakage current.

(10) When CV_DD power is "ON", the pin bus-holders are disabled. For more detailed information, see Section 5.7.2.5, Digital I/O Behavior When Core Power (CV_DD) is Down.

(11) This parameter specifies the maximum strength of the Bus Holder and is needed to calculate the minimum strength of external pull-ups and pull-downs.

5.4 Handling Ratings

		MIN	MAX	UNIT
Storage temperature range, T_stg	(default)	–65	150	ºC
ESD Stress Voltage⁽⁴⁾	Human Body Model (HBM)⁽⁵⁾	0	> 1000	V
	Charged Device Model (CDM)⁽⁶⁾	0	> 250	V

Section 5.5 shows the thermal resistance characteristics for the PBGA–ZHH mechanical package.

5.5 Thermal Characteristics

			°C/W⁽¹⁾	AIR FLOW (m/s)⁽²⁾
RT_JC	Junction-to-case	1S0P	12.53	N/A
RT_JB	Junction-to-board	2S2P	38	N/A
RT_JA	Junction-to-free air	2S2P	50	0.00
Psi_JT	Junction-to-package top	2S2P	0.49	0.00
Psi_JB	Junction-to-board	2S2P	37.4	0.00

(1) These measurements were conducted in a JEDEC-defined 1S0P/2S2P system and will change based on environment as well as application. For more information, see these EIA/JEDEC standards – EIA/JESD51-2, Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air) and JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages.

(2) m/s = meters per second

5.6 Power-On Hours

Over Operating Case Temperature Range (Unless Otherwise Noted)

Device Operating Life
Power-On Hours (POH) ⁽¹⁾

DSP Operating Frequency (SYSCLK ) ≤100 MHz

<70 °C

100,000 POH

(1) This information is provided solely for your convenience and does not extend or modify the warranty provided under TI’s standard terms and conditions for TI semiconductor products.

5.7 Timing and Switching Characteristics

5.7.1 Parameter Information

Figure 5-1 3.3-V Test Load Circuit for AC Timing Measurements

The load capacitance value stated is only for characterization and measurement of AC timing signals. This load capacitance value does not indicate the maximum load the device is capable of driving.

5.7.1.1 1.8-V, 2.5-V, 2.75-V, and 3.3-V Signal Transition Levels

All rise and fall transition timing parameters are referenced to V_IL MAX and V_IH MIN for input clocks, V_OL MAX and V_OH MIN for output clocks.

Figure 5-2 Rise and Fall Transition Time Voltage Reference Levels

5.7.1.2 3.3-V Signal Transition Rates

All timings are tested with an input edge rate of 4 volts per nanosecond (4 V/ns).

5.7.1.3 Timing Parameters and Board Routing Analysis

The timing parameter values specified in this data manual do not include delays by board routing. As a good board design practice, such delays must always be taken into account. Timing values may be adjusted by increasing or decreasing such delays. TI recommends utilizing the available I/O buffer information specification (IBIS) models to analyze the timing characteristics correctly. To properly use IBIS models to attain accurate timing analysis for a given system, see the Using IBIS Models for Timing Analysis application report (literature number SPRA839). If needed, external logic hardware such as buffers may be used to compensate any timing differences.

5.7.2 Power Supplies

5.7.2.1 Power Considerations for C5535 and C5534

The device provides several means of managing power consumption.

To minimize power consumption, the device divides its circuits into nine main isolated supply domains:

LDOI (LDOs and Bandgap Power Supply)
Analog POR, SAR⁽¹⁾, and PLL (V_{DDA_ANA} and V_{DDA_PLL}) ⁽¹⁾
RTC Core (CV_DDRTC)

Note: CV_DDRTC must always be powered by an external power source and none of the on-chip LDOs can be used to power CV_DDRTC.

Digital Core (CV_DD)
USB Core (USB_ V_DD1P3 and USB_V_DDA1P3)
USB PHY and USB PLL (USB_V_DDOSC, USB_V_DDA3P3, and USB_V_DDPLL)
RTC I/O (DV_DDRTC)
Rest of the I/O (DV_DDIO)

(1) SAR applies to only TMS320C5535.

5.7.2.1.1 LDO Configuration

The device includes Low-Dropout Regulators (LDOs) which can be used to regulate the power supplies of the analog PLL and SAR ADC⁽¹⁾ and Power Management (ANA_LDO), Digital Core (DSP_LDO), and USB Core (USB_LDO).

These LDOs are controlled by a combination of pin configuration and register settings. For more detailed information see the following sections.

5.7.2.1.1.1 LDO Inputs

The LDOI pins (B10, B14, C14) provide power to the internal Analog LDO, DSP LDO, USB LDO, the bandgap reference generator, and some I/O input pins, and can range from 1.8 V to 3.6 V. The bandgap provides accurate voltage and current references to the POR, LDOs, PLL, and SAR⁽¹⁾; therefore, for proper device operation, power must always be applied to the LDOI pins even if the LDO outputs are not used.

5.7.2.1.1.2 LDO Outputs

The ANA_LDOO pin (B9) is the output of the internal ANA_LDO and can provide regulated 1.3 V power of up to 4 mA. The ANA_LDOO pin is intended to be connected, on the board, to the V_{DDA_ANA} and V_{DDA_PLL} pins to provide a regulated 1.3 V to the 10-bit SAR ADC, Power Management Circuits and System PLL. V_{DDA_ANA} and V_{DDA_PLL} may be powered by this LDO output, which is recommended, to take advantage of the device's power management techniques, or by an external power supply. The ANA_LDO cannot be disabled individually (see Section 5.7.2.1.1.3, LDO Control).

The DSP_LDOO pin (A13) is the output of the internal DSP_LDO and provides software-selectable regulated 1.3 V or regulated 1.05 V power of up to 250 mA. The DSP_LDOO pin is intended to be connected, on the board, to the CV_DD pins. In this configuration, the DSP_LDO_EN pin must be tied to the board V_SS, thus enabling the DSP_LDO. Optionally, the CV_DD pins may be powered by an external power supply; in this configuration the DSP_LDO_EN pin must be tied (high) to LDOI, disabling DSP_LDO. The DSP_LDO_EN also affects how reset is generated to the chip (for more details, see the DSP_LDO_EN pin description in Table 4-15, Regulators and Power Management Signal Descriptions). When the DSP_LDO is disabled, its output pin is in a high-impedance state. Note: DSP_LDO_EN is not intended to be changed dynamically.

When DSP_LDO comes out of reset, it is enabled to 1.3 V for the bootloader to operate. For the 50-MHz devices, DSP_LDO must be programmed to 1.05 V to match the core voltage, CV_DD, for proper operation after reset.

The USB_LDOO pin (D13 ) is the output of the internal USB_LDO and provides regulated 1.3 V, software-switchable (on and off) power of up to 25 mA. The USB_LDOO pin is intended to be connected, on the board, to the USB_V_DD1P3 and USB_V_DDA1P3 pins to provide power to portions of the USB. Optionally, the USB_V_DD1P3 and USB_V_DDA1P3 may be powered by an external power supply and the USB_LDO can be left disabled. When the USB_LDO is disabled, its output pin is in a high-impedance state.

5.7.2.1.1.3 LDO Control

All LDOs can be simultaneously disabled via software by writing to either the BG_PD bit or the LDO_PD bit in the RTCPMGT register (see Figure 5-3). When the LDOs are disabled via this mechanism, the only way to re-enable them is by asserting the WAKEUP signal pin (which must also have been previously enabled to allow wakeup), orby a previously enabled and configured RTC alarm, orby cycling power to the CV_DDRTC pin.

ANA_LDO: The ANA_LDO is only disabled by the BG_PD and the LDO_PD mechanism described above. Otherwise, it is always enabled.

DSP_LDO: The DSP_LDO can be statically disabled by the DSP_LDO_EN pin as described in Section 5.7.2.1.1.2, LDO Outputs. The DSP_LDO can be also dynamically disabled via the BG_PD and the LDO_PD mechanism described above. The DSP_LDO can change its output voltage dynamically by software via the DSP_LDO_V bit in the LDOCNTL register (see Figure 5-4). The DSP_LDO output voltage is set to 1.3 V at reset.

For the 50 -MHz devices, DSP_LDO must be programmed to 1.05 V to match the core voltage, CV_DD, for proper operation after reset.

USB_LDO: The USB_LDO can be independently and dynamically enabled or disabled by software via the USB_LDO_EN bit in the LDOCNTL register (see Figure 5-4). The USB _LDO is disabled at reset.

Table 5-3 shows the ON and OFF control of each LDO and its register control bit configurations.

Figure 5-3 RTC Power Management Register (RTCPMGT) [1930h]

15	14	13	12	11	10	9	8
Reserved
R-0

7	6	5	4	3	2	1	0
Reserved			WU_DOUT	WU_DIR	BG_PD	LDO_PD	RTCCLKOUTEN
			R/W-1	R/W-0	R/W-0	R/W-0	R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-1 RTCPMGT Register Bit Descriptions

BIT	NAME	DESCRIPTION
15:5	RESERVED	Reserved. Read-only, writes have no effect.
4	WU_DOUT	Wakeup output, active low, open-drain. 0 = WAKEUP pin driven low. 1 = WAKEUP pin is in high-impedance (Hi-Z).
3	WU_DIR	Wakeup pin direction control. 0 = WAKEUP pin configured as a input. 1 = WAKEUP pin configured as a output. Note: When the WAKEUP pin is configured as an input, it is active high. When the WAKEUP pin is configured as an output, is an open-drain that is active low and must be externally pulled-up via a 10-kΩ resistor to DV_DDRTC. WU_DIR must be configured as an input to allow the WAKEUP pin to wake the device up from idle modes.
2	BG_PD	Bandgap, on-chip LDOs, and the analog POR power down bit. This bit shuts down the on-chip LDOs (ANA_LDO, DSP_LDO, and USB_LDO), the Analog POR, and Bandgap reference. BG_PD and LDO_PD are only intended to be used when the internal LDOs supply power to the chip. If the internal LDOs are bypassed and not used then the BG_PD and LDO_PD power down mechanisms should not be used since POR gets powered down and the POWERGOOD signal is not generated properly. After this bit is asserted, the on-chip LDOs, Analog POR, and the Bandgap reference can be re-enabled by the WAKEUP pin (high) or the RTC alarm interrupt. The Bandgap circuit will take about 100 msec to charge the external 0.1 μF capacitor via the internal 326-kΩ resistor. 0 = On-chip LDOs, Analog POR, and Bandgap reference are enabled. 1 = On-chip LDOs, Analog POR, and Bandgap reference are disabled (shutdown).
1	LDO_PD	On-chip LDOs and Analog POR power down bit. This bit shuts down the on-chip LDOs (ANA_LDO, DSP_LDO, and USB_LDO) and the Analog POR. BG_PD and LDO_PD are only intended to be used when the internal LDOs supply power to the chip. If the internal LDOs are bypassed and not used then the BG_PD and LDO_PD power down mechanisms should not be used since POR gets powered down and the POWERGOOD signal is not generated properly. After this bit is asserted, the on-chip LDOs and Analog POR can be re-enabled by the WAKEUP pin (high) or the RTC alarm interrupt. This bit keeps the Bandgap reference turned on to allow a faster wake-up time with the expense power consumption of the Bandgap reference. 0 = On-chip LDOs and Analog POR are enabled. 1 = On-chip LDOs and Analog POR are disabled (shutdown).
0	RTCCLKOUTEN	Clockout output enable bit. 0 = Clock output disabled. 1 = Clock output enabled.

Figure 5-4 LDO Control Register (LDOCNTL) [7004h]

15	14	13	12	11	10	9	8
Reserved
R-0

7	6	5	4	3	2	1	0
Reserved						DSP_LDO_V	USB_LDO_EN
R-0						R/W-0	R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-2 LDOCNTL Register Bit Descriptions

BIT	NAME	DESCRIPTION
15:2	Reserved	Reserved. Read-only, writes have no effect.
1	DSP_LDO_V	DSP_LDO voltage select bit. 0 = DSP_LDOO is regulated to 1.3 V. 1 = DSP_LDOO is regulated to 1.05 V Note: For the 50 -MHz devices, DSP_LDO must be programmed to 1.05 V to match the core voltage, CV_DD, for proper operation after reset.
0	USB_LDO_EN	USB_LDO enable bit. 0 = USB_LDO output is disabled. USB_LDOO pin is placed in high-impedance (Hi-Z) state. 1 = USB_LDO output is enabled. USB_LDOO is regulated to 1.3 V.

BIT

NAME

DESCRIPTION

15:2

Reserved

Reserved. Read-only, writes have no effect.

DSP_LDO_V

DSP_LDO voltage select bit.

0 = DSP_LDOO is regulated to 1.3 V.

1 = DSP_LDOO is regulated to 1.05 V

Note: For the 50 -MHz devices, DSP_LDO must be programmed to 1.05 V to match the core voltage, CV_DD, for proper operation after reset.

USB_LDO_EN

USB_LDO enable bit.

0 = USB_LDO output is disabled. USB_LDOO pin is placed in high-impedance (Hi-Z) state.

1 = USB_LDO output is enabled. USB_LDOO is regulated to 1.3 V.

Table 5-3 LDO Controls Matrix

RTCPMGT Register (1930h)		LDOCNTL Register (7004h)	DSP_LDO_EN (Pin C13 )	ANA_LDO	DSP_LDO	USB_LDO
BG_PD Bit	LDO_PD Bit	USB_LDO_EN Bit	DSP_LDO_EN (Pin C13 )	ANA_LDO	DSP_LDO	USB_LDO
1	Don't Care	Don't Care	Don't Care	OFF	OFF	OFF
Don't Care	1	Don't Care	Don't Care	OFF	OFF	OFF
0	0	0	Low	ON	ON	OFF
0	0	0	High	ON	OFF	OFF
0	0	1	Low	ON	ON	ON

5.7.2.2 Power Considerations for C5533

The device provides several means of managing power consumption.

To minimize power consumption, the device divides its circuits into nine main isolated supply domains:

LDOI (LDOs and Bandgap Power Supply)
Analog POR and PLL (V_{DDA_ANA} and V_{DDA_PLL})
RTC Core (CV_DDRTC)
Digital Core (CV_DD)
USB Core (USB_ V_DD1P3 and USB_V_DDA1P3)
USB PHY and USB PLL (USB_V_DDOSC, USB_V_DDA3P3, and USB_V_DDPLL)
RTC I/O (DV_DDRTC)
Rest of the I/O (DV_DDIO)

5.7.2.2.1 LDO Configuration

The device includes two Low-Dropout Regulators (LDOs) which can be used to regulate the power supplies of the analog PLL and Power Management (ANA_LDO) and USB Core (USB_LDO).

These LDOs are controlled by a combination of pin configuration and register settings. For more detailed information see the following sections.

5.7.2.2.1.1 LDO Inputs

The LDOI pins (B10, B14, C14) provide power to the internal Analog and USB LDOs, the bandgap reference generator, and some I/O input pins, and can range from 1.8 V to 3.6 V. The bandgap provides accurate voltage and current references to the POR, LDOs, and PLL; therefore, for proper device operation, power must always be applied to the LDOI pins even if the LDO outputs arenot used.

5.7.2.2.1.2 LDO Outputs

The ANA_LDOO pin (B9) is the output of the internal ANA_LDO and can provide regulated 1.3 V power of up to 4 mA. The ANA_LDOO pin is intended to be connected, on the board, to the V_{DDA_ANA} and V_{DDA_PLL} pins to provide a regulated 1.3 V to the Power Management Circuits and System PLL. V_{DDA_ANA} and V_{DDA_PLL} may be powered by this LDO output, which is recommended, to take advantage of the device's power management techniques, or by an external power supply. The ANA_LDO cannot be disabled individually (see Section 5.7.2.1.1.3, LDO Control).

The USB_LDOO pin (D13) is the output of the internal USB_LDO and provides regulated 1.3 V, software-switchable (on and off) power of up to 25 mA. The USB_LDOO pin is intended to be connected, on the board, to the USB_V_DD1P3 and USB_V_DDA1P3 pins to provide power to portions of the USB. Optionally, the USB_V_DD1P3 and USB_V_DDA1P3 may be powered by an external power supply and the USB_LDO can be left disabled. When the USB_LDO is disabled, its output pin is in a high-impedance state.

5.7.2.2.1.3 LDO Control

Both LDOs can be simultaneously disabled via software by writing to either the BG_PD bit or the LDO_PD bit in the RTCPMGT register (see Figure 5-3). When the LDOs are disabled via this mechanism, the only way to re-enable them is by asserting the WAKEUP signal pin (which must also have been previously enabled to allow wakeup), or by a previously enabled and configured RTC alarm, or by cycling power to the CV_DDRTC pin.

ANA_LDO: The ANA_LDO is only disabled by the BG_PD and the LDO_PD mechanism described above. Otherwise, it is always enabled.

USB_LDO: The USB_LDO can be independently and dynamically enabled or disabled by software via the USB_LDO_EN bit in the LDOCNTL register (see Figure 5-4). The USB _LDO is disabled at reset.

Table 5-3 shows the ON and OFF control of each LDO and its register control bit configurations.

Figure 5-5 RTC Power Management Register (RTCPMGT) [1930h]

15	14	13	12	11	10	9	8
Reserved
R-0

7	6	5	4	3	2	1	0
Reserved			WU_DOUT	WU_DIR	BG_PD	LDO_PD	RTCCLKOUTEN
			R/W-1	R/W-0	R/W-0	R/W-0	R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-4 RTCPMGT Register Bit Descriptions

BIT	NAME	DESCRIPTION
15:5	RESERVED	Reserved. Read-only, writes have no effect.
4	WU_DOUT	Wakeup output, active low, open-drain. 0 = WAKEUP pin driven low. 1 = WAKEUP pin is in high-impedance (Hi-Z).
3	WU_DIR	Wakeup pin direction control. 0 = WAKEUP pin configured as a input. 1 = WAKEUP pin configured as a output. Note: When the WAKEUP pin is configured as an input, it is active high. When the WAKEUP pin is configured as an output, is an open-drain that is active low and must be externally pulled-up via a 10-kΩ resistor to DV_DDRTC. WU_DIR must be configured as an input to allow the WAKEUP pin to wake the device up from idle modes.
2	BG_PD	Bandgap, on-chip LDOs, and the analog POR power down bit. This bit shuts down the on-chip LDOs (ANA_LDO and USB_LDO), the Analog POR, and Bandgap reference. BG_PD and LDO_PD are only intended to be used when the internal LDOs supply power to the chip. If the internal LDOs are bypassed and not used then the BG_PD and LDO_PD power down mechanisms should not be used since POR gets powered down and the POWERGOOD signal is not generated properly. After this bit is asserted, the on-chip LDOs, Analog POR, and the Bandgap reference can be re-enabled by the WAKEUP pin (high) or the RTC alarm interrupt. The Bandgap circuit will take about 100 msec to charge the external 0.1 uF capacitor via the internal 326-kΩ resistor. 0 = On-chip LDOs, Analog POR, and Bandgap reference are enabled. 1 = On-chip LDOs, Analog POR, and Bandgap reference are disabled (shutdown).
1	LDO_PD	On-chip LDOs and Analog POR power down bit. This bit shuts down the on-chip LDOs (ANA_LDO and USB_LDO) and the Analog POR. BG_PD and LDO_PD are only intended to be used when the internal LDOs supply power to the chip. If the internal LDOs are bypassed and not used then the BG_PD and LDO_PD power down mechanisms should not be used since POR gets powered down and the POWERGOOD signal is not generated properly. After this bit is asserted, the on-chip LDOs and Analog POR can be re-enabled by the WAKEUP pin (high) or the RTC alarm interrupt. This bit keeps the Bandgap reference turned on to allow a faster wake-up time with the expense power consumption of the Bandgap reference. 0 = On-chip LDOs and Analog POR are enabled. 1 = On-chip LDOs and Analog POR are disabled (shutdown).
0	RTCCLKOUTEN	Clockout output enable bit. 0 = Clock output disabled. 1 = Clock output enabled.

Figure 5-6 LDO Control Register (LDOCNTL) [7004h]

15	14	13	12	11	10	9	8
Reserved
R-0

7	6	5	4	3	2	1	0
Reserved							USB_LDO_EN
R-0							R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-5 LDOCNTL Register Bit Descriptions

BIT	NAME	DESCRIPTION
15:1	RESERVED	Reserved. Read-only. Writes have no effect.
0	USB_LDO_EN	USB_LDO enable bit. 0 = USB_LDO output is disabled. USB_LDOO pin is placed in high-impedance (Hi-Z) state. 1 = USB_LDO output is enabled. USB_LDOO is regulated to 1.3 V.

Table 5-6 LDO Controls Matrix

RTCPMGT Register (1930h)		LDOCNTL Register (7004h)	DSP_LDO_EN (Pin C13)	ANA_LDO	USB_LDO
BG_PD Bit	LDO_PD Bit	USB_LDO_EN Bit	DSP_LDO_EN (Pin C13)	ANA_LDO	USB_LDO
1	Don't Care	Don't Care	High	OFF	OFF
Don't Care	1	Don't Care	High	OFF	OFF
0	0	0	High	ON	OFF
0	0	0	High	ON	OFF
0	0	1	High	ON	ON

5.7.2.3 Power Considerations for C5532

The device provides several means of managing power consumption.

To minimize power consumption, the device divides its circuits into nine main isolated supply domains:

LDOI (ANA_LDO and Bandgap Power Supply)
Analog POR and PLL (V_{DDA_ANA} and V_{DDA_PLL})
RTC Core (CV_DDRTC)
Digital Core (CV_DD)
RTC I/O (DV_DDRTC)
Rest of the I/O (DV_DDIO)

5.7.2.3.1 LDO Configuration

The device includes one Low-Dropout Regulators (LDO) which can be used to regulate the power supplies of the analog PLL.

5.7.2.3.2 LDO Inputs

The LDOI pins (B10, B14, C14) provide power to the internal Analog LDO, the bandgap reference generator, and some I/O input pins, and can range from 1.8 V to 3.6 V. The bandgap provides accurate voltage and current references to the LDO PLL; therefore, for proper device operation, power must always be applied to the LDOI pins even if the LDO output is not used.

5.7.2.3.3 LDO Outputs

The ANA_LDOO pin (B9) is the output of the internal ANA_LDO and can provide regulated 1.3 V power of up to 4 mA. The ANA_LDOO pin is intended to be connected, on the board, to the VDDA_ANA and VDDA_PLL pins to provide a regulated 1.3 V to the System PLL. VDDA_ANA and VDDA_PLL may be powered by this LDO output. However, when VDDA_PLL requires 1.4 V, VDDA_PLL must be powered externally and ANA_LDO output can provide a regulated 1.3 V, but only to VDDA_ANA, not both.

NOTE

The DSP_LDOO is not supported on TMS320C5532. However, DSP_LDO can be enabled to support the RTC only mode (see Section 5.7.11.1, RTC Only Mode, for details). Otherwise, DSP_LDO must be disabled on this device and the DSP_LDO output pin must be left unconnected. The USB_LDOO is not supported on this device, so the USB_LDO must be left disabled. USB_LDO is disabled at reset, so it does not require any action to disable the USB_LDO. When the USB_LDO is disabled, the USB_LDOO pin is in a high-impedance (Hi-Z) state and must be left unconnected.

5.7.2.4 Power-Supply Sequencing

NOTE

The external reset signal on the RESET pin must be held low until all of the power supplies reach their operating voltage conditions.

The device includes four core voltage-level supplies (CV_DD, CV_DDRTC, USB_V_DD1P3, USB_V_DDA1P3), and four I/O supplies (DV_DDIO, DV_DDRTC, USB_V_DDOSC, and USB_V_DDA3P3).

Some TI power-supply devices include features that facilitate power sequencing—for example, Auto-Track and Slow-Start and Enable features. For more information regarding TI's power management products and suggested devices to power TI DSPs, visit www.ti.com/processorpower.

The device does not require a specific power-up sequence. However, if the DSP_LDO is disabled (DSP_LDO_EN = high) and an external regulator supplies power to the CPU Core (CV_DD), the external reset signal (RESET) must be held asserted until all of the supply voltages reach their valid operating ranges.

The I/O design allows either the core supplies (CV_DD, CV_DDRTC, USB_V_DD1P3, USB_V_DDA1P3) or the I/O supplies (DV_DDIO, DV_DDRTC, USB_V_DDOSC, and USB_V_DDA3P3) to be powered up for an indefinite period of time while the other supply is not powered if the following constraints are met:

All maximum ratings and recommended operating conditions are satisfied.
All warnings about exposure to maximum rated and recommended conditions, particularly junction temperature are satisfied. These apply to power transitions as well as normal operation.
Bus contention while core supplies are powered must be limited to 100 hours over the projected lifetime of the device.
Bus contention while core supplies are powered down does not violate the absolute maximum ratings.

If the USB subsystem is used, the subsystem must be powered up in the following sequence:

USB_V_DDA1P3 and USB_V_DD1P3
USB_V_DDA3P3
USB_V_BUS

If the USB subsystem is not used, the following can be powered off:

USB Core
- USB_V_DD1P3
- USB_V_DDA1P3
USB PHY and I/O Level Supplies
- USB_V_DDOSC
- USB_V_DDA3P3
- USB_V_DDPLL

A supply bus is powered up when the voltage is within the recommended operating range. The supply bus is powered down when the voltage is below that range, either stable or while in transition.

5.7.2.5 Digital I/O Behavior When Core Power (CV_DD) is Down

With some exceptions (listed below), all digital I/O pins on the device have special features to allow powering down of the Digital Core Domain (CV_DD) without causing I/O contentions or floating inputs at the pins (see Figure 5-7). The device asserts the internal signal called HHV high when power has been removed from the Digital Core Domain (CV_DD). Asserting the internal HHV signal causes the following conditions to occur in any order:

All output pin strong drivers to go to the high-impedance (Hi-Z) state
Weak bus holders to be enabled to hold the pin at a valid high or low
The internal pullups or pulldowns (IPUs and IPDs) on the I/O pins will be disabled

The exception pins that do not have this special feature are:

Pins driven by the CV_DDRTC Power Domain [This power domain is "Always On"; therefore, the pins driven by CV_DDRTCdo not need these special features]:
- RTC_XI, RTC_XO, RTC_CLKOUT, and WAKEUP
USB Pins:
- USB_DP, USB_DM, USB_R1, USB_VBUS, USB_MXI, and USB_MXO
Pins for the Analog Block:
- GPAIN[3:0 ], DSP_LDO_EN and BG_CAP

Figure 5-7 Bus Holder I/O Circuit

NOTE

Figure 5-7 shows both a pullup and pulldown but pins have only one, not both.

PI = Pullup and pulldown Inhibit

GZ = Output Enable (active low)

HHV = Described in Section 5.7.2.5

5.7.2.6 Power-Supply Design Considerations

Core and I/O supply voltage regulators should be located close to the DSP (or DSP array) to minimize inductance and resistance in the power delivery path. Additionally, when designing for high-performance applications utilizing the device, the PC board should include separate power planes for core, I/O, V_{DDA_ANA} and V_{DDA_PLL} (which can share the same PCB power plane), and ground; all bypassed with high–quality low–ESL and ESR capacitors.

5.7.2.7 Power-Supply Decoupling

In order to properly decouple the supply planes from system noise, place capacitors (caps) as close as possible to the device. These caps need to be no more than 1.25 cm maximum distance from the device power pins to be effective. Physically smaller caps, such as 0402, are better but need to be evaluated from a yield and manufacturing point-of-view. Parasitic inductance limits the effectiveness of the decoupling capacitors, therefore physically smaller capacitors must be used while maintaining the largest available capacitance value.

Larger caps for each supply can be placed further away for bulk decoupling. Large bulk caps (on the order of 10 μF) should be furthest away, but still as close as possible. Large caps for each supply should be placed outside of the BGA footprint.

As with the selection of any component, verification of capacitor availability over the product's production lifetime must be considered.

The recommended decoupling capacitance for the DSP core supplies should be 1 μF in parallel with 0.01-μF capacitor per supply pin.

5.7.2.8 LDO Input Decoupling

The LDO inputs should follow the same decoupling guidelines as other power-supply pins above.

5.7.2.9 LDO Output Decoupling

The LDO circuits implement a voltage feedback control system which has been designed to optimize gain and stability tradeoffs. As such, there are design assumptions for the amount of capacitance on the LDO outputs. For proper device operation, the following external decoupling capacitors must be used when the on-chip LDOs are enabled:

ANA_LDOO– 1μF
DSP_LDOO – 5μF ~ 10μF
USB_LDOO – 1μF ~ 2μF

5.7.3 Reset

The device has two main types of reset: hardware reset and software reset.

Hardware reset is responsible for initializing all key states of the device. The hardware reset occurs whenever the RESET pin is asserted or when the internal power-on-reset (POR) circuit deasserts an internal signal called POWERGOOD. The device's internal POR is a voltage comparator that monitors the DSP_LDOO pin voltage and generates the internal POWERGOOD signal when the DSP_LDO is enabled externally by the DSP_LDO_EN pin. POWERGOOD is asserted when the DSP_LDOO voltage is above a minimum threshold voltage provided by the bandgap. When the DSP_LDO is disabled (DSP_LDO_EN is high), the internal voltage comparator becomes inactive, and the POWERGOOD signal logic level is immediately set high. The RESET pin and the POWERGOOD signal are internally combined with a logical AND gate to produce an (active low) hardware reset (see Figure 5-8, Power-On Reset Timing Requirements and Figure 5-9, Reset Timing Requirements).

There are two types of software reset: the CPU's software reset instruction and the software control of the peripheral reset signals. For more information on the CPU's software reset instruction, see the TMS320C55x CPU 3.0 CPU Reference Guide (literature number: SWPU073). In all the device documentation, all references to "reset" refer to hardware reset. Any references to software reset will explicitly state software reset.

The device RTC has one additional type of reset, a power-on-reset (POR) for the registers in the RTC core. This POR monitors the voltage of CV_DDRTC and resets the RTC registers when power is first applied to the RTC core.

5.7.3.1 Power-On Reset (POR) Circuits

The device includes two power-on reset (POR) circuits, one for the RTC (RTC POR) and another for the rest of the chip (MAIN POR).

5.7.3.1.1 RTC Power-On Reset (POR)

The RTC POR ensures that the flip-flops in the CV_DDRTC power domain have an initial state upon powerup. In particular, the RTCNOPWR register is reset by this POR and is used to indicate that the RTC time registers need to be initialized with the current time and date when power is first applied.

5.7.3.1.2 Main Power-On Reset (POR)

The device includes an analog power-on reset (POR) circuit that keeps the DSP in reset until specific voltages have reached predetermined levels. When the DSP_LDO is enabled externally by the DSP_LDO_EN pin, the output of the POR circuit, POWERGOOD, is held low until the following conditions are satisfied:

LDOI is powered and the bandgap is active for at least approximately 8 ms
VDD_ANA is powered for at least approximately 4 ms
DSP_LDOO is above a threshold of approximately 950 mV

Note: The POR comparator has hysteresis, so the threshold voltage becomes approximately 850 mV after POWERGOOD signal is set high.

Once these conditions are met, the internal POWERGOOD signal is set high. The POWERGOOD signal is internally combined with the RESET pin signal, via an AND-gate, to produce the DSP subsystem's global reset. This global reset is the hardware reset for the whole chip, except the RTC. When the global reset is deasserted (high), the boot sequence starts. For more detailed information on the boot sequence, see Section 6.4.1, Boot Sequence.

When the DSP_LDO is disabled (DSP_LDO_EN pin = 1), the voltage monitoring on the DSP_LDOO pin is de-activated and the POWERGOOD signal is immediately set high. The RESET pin will be the sole source of hardware reset.

5.7.3.1.3 Reset Pin (RESET)

The device can receive an external reset signal on the RESET pin. As specified above in Section 5.7.3.1.2, Main Power-On Reset, the RESET pin is combined with the internal POWERGOOD signal, that is generated by the MAIN POR, via an AND-gate. The output of the AND gate provides the hardware reset to the chip. The RESET pin may be tied high and the MAIN POR can provide the hardware reset in case DSP_LDO is enabled (DSP_LDO_EN = 0), but an external hardware reset must be provided via the RESET pin when the DSP_LDO is disabled (DSP_LDO_EN = 1).

Once the hardware reset is applied, the system clock generator is enabled and the DSP starts the boot sequence. For more information on the boot sequence, see Section 6.4.1, Boot Sequence.

5.7.3.2 Pin Behavior at Reset

During normal operation, pins are controlled by the respective peripheral selected in the External Bus Selection Register (EBSR) register. During power-on reset and reset, the behavior of the output pins changes and is categorized as follows:

	High Group: LCD_RS/SPI_CS3
	Low Group:LCD_EN_RDB/SPI_CLK, SD0_CLK/I2S0_CLK/GP[0], SD1_CLK/I2S1_CLK/GP[6]
	Z Group: EMU[1:0], SCL, SDA, LCD_D[0]/SPI_RX, LCD_D[1]/SPI_TX, LCD_D[10]/I2S2_RX/GP[20]/SPI_RX, LCD_D[11]/I2S2_DX/GP[27]/SPI_TX, LCD_D[12]/UART_RTS/GP[28]/I2S3_CLK, LCD_D[13]/UART_CTS/GP[29]/I2S3_FS, LCD_D[14]/UART_RXD/GP[30]/I2S3_RX, LCD_D[15]/UART_TXD/GP[31]/I2S3_DX, LCD_D[2]/GP[12], LCD_D[3]/GP[13], LCD_D[4]/GP[14], LCD_D[5]/GP[15], LCD_D[6]/GP[16], LCD_D[7]/GP[17], LCD_D[8]/I2S2_CLK/GP[18]/SPI_CLK, LCD_D[9] I2S2_FS/GP[19]/SPI_CS0, RTC_CLKOUT, SD0_CMD/I2S0_FS/GP[1], SD0_D0/I2S0_DX/GP[2], SD0_D1/I2S0_RX/GP[3], SD0_D2/GP[4], SD0_D3/GP[5], SD1_CMD/I2S1_FS/GP[7], SD1_D0/I2S1_DX/GP[8], SD1_D1/I2S1_RX/GP[9], SD1_D2/GP[10], SD1_D3/GP[11], TDO, WAKEUP
	CLKOUT Group: CLKOUT, LCD_CS1_E1/SPI_CS1
	SYNCH 0→1 Group: LCD_CS0_E0/SPI_CS0, LCD_RW_WRB/SPI_CS2
	SYNCH x→1 Group: XF

5.7.3.3 Reset Electrical Data and Timing

Table 5-7 Timing Requirements for Reset⁽¹⁾ (see Figure 5-8 and Figure 5-9)

NO.			CV_DD = 1.05 V		CV_DD = 1.3 V		UNIT
NO.			MIN	MAX	MIN	MAX	UNIT
1	t_w(RSTL)	Pulse duration, RESET low	3P		3P		ns

(1) P = 1/SYSCLK clock frequency in ns. For example, if SYSCLK = 12 MHz, use P = 83.3 ns. In IDLE3 mode the system clock generator is bypassed and the SYSCLK frequency is equal to either CLKIN or the RTC clock frequency depending on CLK_SEL.

Figure 5-8 Power-On Reset Timing Requirements

Figure 5-9 Reset Timing Requirements

5.7.3.4 Configurations at Reset

Some device configurations are determined at reset. The following subsections give more details.

5.7.3.4.1 Device and Peripheral Configurations at Device Reset

Table 5-8 summarizes the device boot and configuration pins that are required to be statically tied high, tied low, or remain unconnected during device operation. For proper device operation, a device reset must be initiated after changing any of these pin functions.

Table 5-8 Default Functions Affected by Device Configuration Pins

CONFIGURATION PINS	SIGNAL NO.	IPU and IPD	FUNCTIONAL DESCRIPTION
DSP_LDO_EN	C13	–	DSP_LDO enable input. This signal is not intended to be dynamically switched. 0 = DSP_LDO is enabled. The internal DSP LDO is enabled to regulate power on the DSP_LDOO pin at either 1.3 V or 1.05 V according to the DSP_LDO_V bit in the LDOCNTL register, see Figure 5-4). At power-on-reset, the internal POR monitors the DSP_LDOO pin voltage and generates the internal POWERGOOD signal when the DSP_LDO voltage is above a minimum threshold voltage. The internal device reset is generated by the AND of POWERGOOD and the RESET pin. Note: For the 50-MHz devices, DSP_LDO must be programmed to 1.05 V to match the core voltage, CV_DD, for proper operation after reset. 1 = DSP_LDO is disabled and the DSP_LDOO pin is in a high-impedance (Hi-Z) state. The internal voltage monitoring on the DSP_LDOO is bypassed and the internal POWERGOOD signal is immediately set high. The RESET pin will act as the sole reset source for the device. If an external power supply is used to provide power to CV_DD, then DSP_LDO_EN must be tied to LDOI, DSP_LDOO must be left unconnected, and the RESET pin must be asserted appropriately for device initialization after powerup. Note: To pullup this pin, connect it to the same supply as LDOI pins.
CLK_SEL	D1	–	Clock input select. 0 = 32-kHz on-chip oscillator drives the RTC timer and the system clock generator. CLKIN is ignored. 1 = CLKIN drives the system clock generator and the 32-kHz on-chip oscillator drives only the RTC timer. This pin is not allowed to change during device operation; it must be tied to DV_DDIO or GND at the board.

CONFIGURATION PINS

SIGNAL NO.

IPU and IPD

FUNCTIONAL DESCRIPTION

DSP_LDO_EN

C13

–

DSP_LDO enable input.

This signal is not intended to be dynamically switched.

0 = DSP_LDO is enabled. The internal DSP LDO is enabled to regulate power on the DSP_LDOO pin at either 1.3 V or 1.05 V according to the DSP_LDO_V bit in the LDOCNTL register, see Figure 5-4). At power-on-reset, the internal POR monitors the DSP_LDOO pin voltage and generates the internal POWERGOOD signal when the DSP_LDO voltage is above a minimum threshold voltage. The internal device reset is generated by the AND of POWERGOOD and the RESET pin.

Note: For the 50-MHz devices, DSP_LDO must be programmed to 1.05 V to match the core voltage, CV_DD, for proper operation after reset.

1 = DSP_LDO is disabled and the DSP_LDOO pin is in a high-impedance (Hi-Z) state. The internal voltage monitoring on the DSP_LDOO is bypassed and the internal POWERGOOD signal is immediately set high. The RESET pin will act as the sole reset source for the device. If an external power supply is used to provide power to CV_DD, then DSP_LDO_EN must be tied to LDOI, DSP_LDOO must be left unconnected, and the RESET pin must be asserted appropriately for device initialization after powerup.

Note: To pullup this pin, connect it to the same supply as LDOI pins.

CLK_SEL

–

Clock input select.
0 = 32-kHz on-chip oscillator drives the RTC timer and the system clock generator. CLKIN is ignored.
1 = CLKIN drives the system clock generator and the 32-kHz on-chip oscillator drives only the RTC timer.

This pin is not allowed to change during device operation; it must be tied to DV_DDIO or GND at the board.

For proper device operation, external pullup and pulldown resistors may be required on these device configuration pins. For discussion on situations where external pullup and pulldown resistors are required, see Section 5.7.17.1.1, Pullup and Pulldown Resistors.

This device also has RESERVED pins that need to be configured correctly for proper device operation (statically tied high, tied low, or remain unconnected at all times). For more details on these pins, see Table 4-16, Reserved and No Connects Signal Descriptions.

5.7.3.5 Configurations After Reset

The following sections provide details on configuring the device after reset. Multiplexed pin functions are selected by software after reset. For more details on multiplexed pin function control, see Section 4.3, Pin Multiplexing.

5.7.3.5.1 External Bus Selection Register (EBSR)

The External Bus Selection Register (EBSR) determines the mapping of the LCD controller, I2S2, I2S3, UART, SPI, and GPIO signals to 21 signals of the external parallel port pins. The EBSR also determines the mapping of the I2S or SD ports to serial port 1 pins and serial port 2 pins. The EBSR register is located at port address 1C00h. Once the bit fields of this register are changed, the routing of the signals takes place on the next CPU clock cycle.

Before modifying the values of the external bus selection register, you must clock gate all affected peripherals through the Peripheral Clock Gating Control Register. After the external bus selection register has been modified, you must reset the peripherals before using them through the Peripheral Software Reset Counter Register.

Figure 5-10 External Bus Selection Register (EBSR) [1C00h]

15	14	13	12	11	10	9	8
Reserved	PPMODE			SP1MODE		SP0MODE
R-0	R/W-000			R/W-00		R/W-00

7	6	5	4	3	2	1	0
Reserved	Reserved
R-0	R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5-9 EBSR Register Bit Descriptions

BIT	NAME	DESCRIPTION
15	RESERVED	Reserved. Read-only, writes have no effect.
14:12	PPMODE	Parallel Port Mode Control Bits. These bits control the pin multiplexing of the LCD Controller, SPI, UART, I2S2, I2S3, and GP[31:27, 20:18] pins on the parallel port. For more details, see Table 4-19, LCD Controller, SPI, UART, I2S2, I2S3, and GP[31:27, 20:18] Pin Multiplexing.
		000 = Mode 0 (16-bit LCD Controller). All 21 signals of the LCD Bridge module are routed to the 21 external signals of the parallel port.
		001 = Mode 1 (SPI, GPIO, UART, and I2S2). 7 signals of the SPI module, 6 GPIO signals, 4 signals of the UART module and 4 signals of the I2S2 module are routed to the 21 external signals of the parallel port.
		010 = Mode 2 (8-bit LCD Controller and GPIO). 8 bits of pixel data of the LCD Controller module and 8 GPIO are routed to the 21 external signals of the parallel port.
		011 = Mode 3 (8-bit LCD Controller, SPI and I2S3). 8 bits of pixel data of the LCD Controller module, 4 signals of the SPI module and 4 signals of the I2S3 module are routed to the 21 external signals of the parallel port.
		100 = Mode 4 (8-bit LCD Controller, I2S2 and UART). 8 bits of pixel data of the LCD Controller module, 4 signals of the I2S2 module and 4 signals of the UART module are routed to the 21 external signals of the parallel port.
		101 = Mode 5 (8-bit LCD Controller, SPI and UART). 8 bits of pixel data of the LCD Controller module, 4 signals of the SPI module and 4 signals of the UART module are routed to the 21 external signals of the parallel port.
		110 = Mode 6 (SPI, I2S2, I2S3, and GPIO). 7 signals of the SPI module, 4 signals of the I2S2 module, 4 signals of the I2S3 module, and 6 GPIO are routed to the 21 external signals of the parallel port.
		111 = Reserved.
11:10	SP1MODE	Serial Port 1 Mode Control Bits. The bits control the pin multiplexing of the SD1, I2S1, and GPIO pins on serial port 1. For more details, see Table 4-20, SD1, I2S1, and GP[11:6] Pin Multiplexing.
		00 = Mode 0 (SD1). All 6 signals of the SD1 module are routed to the 6 external signals of the serial port 1.
		01 = Mode 1 (I2S1 and GP[11:10]). 4 signals of the I2S1 module and 2 GP[11:10] signals are routed to the 6 external signals of the serial port 1.
		10 = Mode 2 (GP[11:6]). 6 GPIO signals (GP[11:6]) are routed to the 6 external signals of the serial port 1.
		11 = Reserved.
9:8	SP0MODE	Serial Port 0 Mode Control Bits. The bits control the pin multiplexing of the SD0, I2S0, and GPIO pins on serial port 0. For more details, see Section 4.3.3, SD0, I2S0, and GP[5:0] Pin Multiplexing.
		00 = Mode 0 (SD0). All 6 signals of the SD0 module are routed to the 6 external signals of the serial port 0.
		01 = Mode 1 (I2S0 and GP[5:0]). 4 signals of the I2S0 module and 2 GP[5:4] signals are routed to the 6 external signals of the serial port 0.
		10 = Mode 2 (GP[5:0]). 6 GPIO signals (GP[5:0]) are routed to the 6 external signals of the serial port 0.
		11 = Reserved.
7	RESERVED	Reserved. Read-only, writes have no effect.
6	RESERVED	Reserved. Read-only, writes have no effect.
5	RESERVED	Reserved
4	RESERVED	Reserved
3	RESERVED	Reserved
2	RESERVED	Reserved
1	RESERVED	Reserved
0	RESERVED	Reserved

5.7.3.5.2 LDO Control Register [7004h]

When the DSP_LDO is enabled by the DSP_LDO_EN pin [C13], by default, the DSP_LDOO voltage is set to 1.3 V. The DSP_LDOO voltage can be programmed to be either 1.05 V or 1.3 V via the DSP_LDO_V bit (bit 1) in the LDO Control Register (LDOCNTL).

For the 50-MHz devices, DSP_LDO must be programmed to 1.05 V to match the core voltage, CV_DD, for proper operation after reset.

At reset, the USB_LDO is turned off. The USB_LDO can be enabled via the USBLDOEN bit (bit 0) in the LDOCNTL register.

For more detailed information on the LDOs, see Section 5.7.2.1.1LDO Configuration.

5.7.3.5.3 USB System Control Registers (USBSCR) [1C32h]

After reset, by default, the CPU performs 16-bit accesses to the USB register and data space. To perform 8-bit accesses to the USB data space, the user must set the BYTEMODE bits to 01b for the "high byte" or 10b for the "low byte" in the USB System Control Register (USBSCR).

5.7.3.5.4 Peripheral Clock Gating Control Registers (PCGCR1 and PCGCR2) [1C02h and 1C03h]

After hardware reset, the DSP executes the on-chip bootloader from ROM. As the bootloader executes, it selectively enables the clock of the peripheral being queried for a valid boot. If a valid boot source is not found, the bootloader disables the clock to that peripheral and moves on to the next peripheral in the boot order. After the boot process is complete, all of the peripheral clocks will be off and all domains in the ICR, except for the CPU domain, will be idled (this includes the MPORT and HWA). The user must enable the clocks to the peripherals and CPU ports that are going to be used. The peripheral clock gating control registers (PCGCR1 and PCGCR2) are used to enable and disable the peripheral clocks.

5.7.3.5.5 Pullup and Pulldown Inhibit Registers (PDINHIBR1, 2, and 3) [1C17h, 1C18h, and 1C19h]

Each internal pullup and pulldown (IPU and IPD) resistor on the device DSP, except for the IPD on TRST, can be individually controlled through the IPU and IPD registers (PDINHIBR1 [1C17h] , PDINHIBR2 [1C18h], and PDINHIBR3 [1C19h]). To minimize power consumption, internal pullup or pulldown resistors must be disabled in the presence of an external pullup or pulldown resistor or external driver. Section 5.7.17.1.1, Pullup and Pulldown Resistors, describes other situations in which an pullup and pulldown resistors are required.

When CV_DD is powered down, pullup and pulldown resistors will be forced disabled and an internal bus-holder will be enabled. For more detailed information, see Section 5.7.2.5, Digital I/O Behavior When Core Power (CV_DD) is Down.

5.7.3.5.6 Output Slew Rate Control Register (OSRCR) [1C16h]

To provide the lowest power consumption setting, the DSP has configurable slew rate control on the CLKOUT output pin. The output slew rate control register (OSRCR) is used to set a subset of the device I/O pins, namely the CLKOUT pin, to either fast or slow slew rate. The slew rate feature is implemented by staging or delaying turn-on times of the parallel p-channel drive transistors and parallel n-channel drive transistors of the output buffer. In the slow slew rate configuration, the delay is longer, but ultimately the same number of parallel transistors are used to drive the output high or low. Thus, the drive strength is ultimately the same. The slower slew rate control can be used for power savings and has the greatest effect at lower DV_DDIO voltages.

5.7.4 Clock Specifications

5.7.4.1 Recommended Clock and Control Signal Transition Behavior

All clocks and control signals must transition between V_IH and V_IL (or between V_IL and V_IH) in a monotonic manner.

5.7.4.2 Clock Considerations

The system clock, which is used by the CPU and most of the DSP peripherals, is controlled by the system clock generator. The system clock generator features a software-programmable PLL multiplier and several dividers. The clock generator accepts an input reference clock from the CLKIN pin or the output clock of the 32.768-kHz real-time clock (RTC) oscillator. The selection of the input reference clock is based on the state of the CLK_SEL pin. The CLK_SEL pin is required to be statically tied high or low and cannot change dynamically after reset.

In addition, the DSP requires a reference clock for USB applications. The USB reference clock is generated using a dedicated on-chip oscillator with a 12-MHz external crystal connected to the USB_MXI and USB_MXO pins.

The USB reference clock is not required if the USB peripheral is not being used. To completely disable the USB oscillator, connect the USB_MXI pin to ground (V_SS) and leave the USB_MXO pin unconnected. The USB oscillator power pins (USB_V_DDOSC and USB_V_SSOSC) should also be connected to ground.

The RTC oscillator generates a clock when a 32.768-kHz crystal is connected to the RTC_XI and RTC_XO pins. The 32.768-kHz crystal can be disabled if CLKIN is used as the clock source for the DSP. However, when the RTC oscillator is disabled, the RTC peripheral will not operate and the RTC registers (I/O address range 1900h – 197Fh) will not be accessible. This includes the RTC power management register (RTCPMGT) which controls the RTCLKOUT and WAKEUP pins. To disable the RTC oscillator, connect the RTC_XI pin to CV_DDRTC and the RTC_XO pin to ground.

For more information on crystal specifications for the RTC oscillator and the USB oscillator, see Section 5.7.4.3.3, External Clock Input From RTC_XI, CLKIN, and USB_MXI Pins.

5.7.4.2.1 Clock Configurations After Device Reset

After reset, the on-chip bootloader programs the system clock generator based on the input clock selected via the CLK_SEL pin.

If CLK_SEL = 0, the bootloader programs the system clock generator and sets the system clock to 12.288 MHz (multiply the 32.768-kHz RTC oscillator clock by 375).

If CLK_SEL = 1, the bootloader bypasses the system clock generator altogether and the system clock is driven by the CLKIN pin. In this case, the CLKIN frequency is expected to be 11.2896 MHz, 12.000 MHz, or 12.288 MHz. The bootloader sets the system PLL to 60 MHz and the SPI module clock to 15 MHz. While the bootloader tries to boot from the USB, the clock generator will be programmed to output approximately 36 MHz.

5.7.4.2.1.1 Device Clock Frequency

After the boot process is complete, the user is allowed to re-program the system clock generator to bring the device up to the desired clock frequency and the desired peripheral clock state (clock gating or not). The user must adhere to various clock requirements when programming the system clock generator. For more information, see Section 5.7.4.3, Clock PLLs.

Note: The on-chip bootloader allows for DSP registers to be configured during the boot process. However, this feature must not be used to change the output frequency of the system clock generator during the boot process. The bootloader also uses Timer0 to calculate the settling time of BG_CAP until executing bootloader code. The bootloader register modification feature must not modify the Timer0 registers.

5.7.4.2.1.2 Peripheral Clock State

The clock and reset state of each of peripheral is controlled through a set of system registers. The peripheral clock gating control registers (PCGCR1 and PCGCR2) are used to enable and disable peripheral clocks. The peripheral software reset counter register (PSRCR) and the peripheral reset control register (PRCR) are used to assert and de-assert peripheral reset signals.

At hardware reset, all of the peripheral clocks are off to conserve power. After hardware reset, the DSP boots via the bootloader code in ROM. During the boot process, the bootloader queries each peripheral to determine if it can boot from that peripheral. In other words, it reads each peripheral searching for a valid boot image file. At that time, the individual peripheral clocks will be enabled for the query and then disabled again when the bootloader is finished with the peripheral. By the time the bootloader releases control to the user code, all peripheral clocks will be off and all domains in the ICR, except the CPU domain, will be idled.

5.7.4.2.1.3 USB Oscillator Control

The USB oscillator is controlled through the USB system control register (USBSCR). To enable the oscillator, the USBOSCDIS and USBOSCBIASDIS bits must be cleared to 0. The user must wait until the USB oscillator stabilizes before proceeding with the USB configuration. The USB oscillator stabilization time is typically 100 μs, with a 10 ms maximum (Note: the startup time is highly dependent on the ESR and capacitive load on the crystal).

5.7.4.3 PLLs

The device DSP uses a software-programmable PLL to generate frequencies required by the CPU, DMA, and peripherals. The reference clock for the PLL is taken from either the CLKIN pin or the RTC on-chip oscillator (as specified through the CLK_SEL pin).

5.7.4.3.1 PLL Device-Specific Information

Table 5-10 PLL Clock Frequency Ranges

CLOCK SIGNAL NAME	CV_DD = 1.05 V V_{DDA_PLL} = 1.3 V		CV_DD = 1.3 V V_{DDA_PLL} = 1.3 V		UNIT
CLOCK SIGNAL NAME	MIN	MAX	MIN	MAX	UNIT
CLKIN⁽¹⁾		11.2896 12 12.288		11.2896 12 12.288	MHz
RTC Clock		32.768		32.768	kHz
PLLIN	32.768	170	32.768	170	kHz
PLLOUT	60	120	60	120	MHz
SYSCLK	0.032768	50	0.032768	100	MHz
PLL_LOCKTIME		4		4	ms

(1) These CLKIN values are used when the CLK_SEL pin = 1.

The PLL has lock time requirements that must be followed. The PLL lock time is the amount of time needed for the PLL to complete its phase-locking sequence. After the maximum PLL_LOCKTIME has passed, the PLL is locked and ready to use.

5.7.4.3.2 Clock PLL Considerations With External Clock Sources

If the CLKIN pin is used to provide the reference clock to the PLL, to minimize the clock jitter a single clean power supply should power both the device and the external clock oscillator circuit. The minimum CLKIN rise and fall times should also be observed. For the input clock timing requirements, see Section 5.7.4.4, Input and Output Clocks Electrical Data and Timing.

Rise and fall times, duty cycles (high and low pulse durations), and the load capacitance of the external clock source must meet the device requirements in this data manual (see Section 5.3, Electrical Characteristics, and Section 5.7.4.4, Input and Output Clocks Electrical Data and Timing.

5.7.4.3.3 External Clock Input From RTC_XI, CLKIN, and USB_MXI Pins

The device DSP includes two options to provide an external clock input to the system clock generator:

Use the on-chip real-time clock (RTC) oscillator with an external 32.768-kHz crystal connected to the RTC_XI and RTC_XO pins.
Use an external 11.2896-, 12.0-, or 12.288-MHz LVCMOS clock input fed into the CLKIN pin that operates at the same voltage as the DV_DDIO supply (1.8-, 2.5-, 2.75-, or 3.3-V).

The CLK_SEL pin determines which input is used as the clock source for the system clock generator. For more details, see Section 5.7.3.4.1, Device and Peripheral Configurations at Device Reset. The crystal for the RTC oscillator is not required if CLKIN is used as the system reference clock; however, the RTC must still be powered by an external power source. None of the on-chip LDOs can power CV_DDRTC. The RTC registers starting at I/O address 1900h will not be accessible without an RTC clock. This includes the RTC Power Management Register which provides control to the on-chip LDOs and WAKEUP and RTC_CLKOUT pins.Section 5.7.4.3.3.1, Real-Time Clock (RTC) On-Chip Oscillator With External Crystal provides more details on using the RTC on-chip oscillator with an external crystal. Section 5.7.4.3.3.2, CLKIN Pin With LVCMOS-Compatible Clock Input provides details on using an external LVCMOS-compatible clock input fed into the CLKIN pin.

Additionally, the USB requires a reference clock generated using a dedicated on-chip oscillator with a 12-MHz external crystal connected to the USB_MXI and USB_MXO pins. The USB reference clock is not required if the USB peripheral is not being used. Section 5.7.4.3.3.3, USB On-Chip Oscillator With External Crystal provides details on using the USB on-chip oscillator with an external crystal.

5.7.4.3.3.1 Real-Time Clock (RTC) On-Chip Oscillator With External Crystal

The on-chip oscillator requires an external 32.768-kHz crystal connected across the RTC_XI and RTC_XO pins, along with two load capacitors, as shown in Figure 5-11. The external crystal load capacitors must be connected only to the RTC oscillator ground pin (V_SSRTC). Do not connect to board ground (V_SS). Position the V_SS lead on the board between RTC_XI and RTC_XO as a shield to reduce direct capacitance between RTC_XI and RTC_XO leads on the board. The CV_DDRTC pin can be connected to the same power supply as CV_DD , or may be connected to a different supply that meets the recommended operating conditions (see Section 5.2, Recommended Operating Conditions), if desired. However, the CV_DDRTC pin must not be supplied by any on-chip LDOs.

Figure 5-11 32.768-kHz RTC Oscillator

The crystal should be in fundamental-mode function, and parallel resonant, with a maximum effective series resistance (ESR) specified in Table 5-11. The load capacitors, C1 and C2, are the total capacitance of the circuit board and components, excluding the IC and crystal. The load capacitors values are usually approximately twice the value of the crystal's load capacitance, CL, which is specified in the crystal manufacturer's datasheet and should be chosen such that the equation is satisfied.

All discrete components used to implement the oscillator circuit must be placed as close as possible to the associated oscillator pins (RTC_XI and RTC_XO) and to the V_SSRTC pin.

Table 5-11 Input Requirements for Crystal on the 32.768-kHz RTC Oscillator

PARAMETER	MIN	NOM	MAX	UNIT
Start-up time (from power up until oscillating at stable frequency of 32.768-kHz)⁽¹⁾	0.2		2	sec
Oscillation frequency		32.768		kHz
ESR			100	kΩ
Maximum shunt capacitance			1.6	pF
Maximum crystal drive			1.0	μW

(1) The startup time is highly dependent on the ESR and the capacitive load of the crystal.

5.7.4.3.3.2 CLKIN Pin With LVCMOS-Compatible Clock Input (Optional)

Note: If CLKIN is not used, the pin must be tied low.

A LVCMOS-compatible clock input of a frequency less than 24 MHz can be fed into the CLKIN pin for use by the DSP system clock generator. The external connections are shown in Figure 5-12 and Figure 5-13. The bootloader assumes that the CLKIN pin is connected to the LVCMOS-compatible clock source with a frequency of 11.2896-, 12.0-, or 12.288-MHz. These frequencies were selected to support boot mode peripheral speeds of 500 kHz for SPI and 400 kHz for I2C and UART. These clock frequencies are achieved by dividing the CLKIN value by 25 for SPI and by 32 for I2C and UART. If a faster external clock is input, then these boot modes will run at faster clock speeds. If the system design utilizes faster peripherals or these boot modes are not used, CLKIN values higher than 12.288 MHz can be used. Note: The CLKIN pin operates at the same voltage as the DV_DDIO supply (1.8-, 2.5-, 2.75-, or 3.3-V).

In this configuration the RTC oscillator can be optionally disabled by connecting RTC_XI to CV_DDRTC and RTC_XO to ground (V_SS). However, when the RTC oscillator is disabled the RTC registers starting at I/O address 1900h will not be accessible. This includes the RTC Power Management Register which provides control to the on-chip LDOs and WAKEUP and RTC_CLKOUT pins.Note: The RTC core must still be powered by an external power source even if the RTC oscillator is disabled. None of the on-chip LDOs can power CV_DDRTC.

For more details on the RTC on-chip oscillator, see Section 5.7.4.3.3.1, Real-Time Clock (RTC) On-Chip Oscillator With External Crystal.

Figure 5-12 LVCMOS-Compatible Clock Input With RTC Oscillator Enabled

Figure 5-13 LVCMOS-Compatible Clock Input With RTC Oscillator Disabled

5.7.4.3.3.3 USB On-Chip Oscillator With External Crystal (Optional)

When using the USB, the USB on-chip oscillator requires an external 12-MHz crystal connected across the USB_MXI and USB_MXO pins, along with two load capacitors, as shown in Figure 5-14. The external crystal load capacitors must be connected only to the USB oscillator ground pin (USB_V_SSOSC). Do not connect to board ground (V_SS). The USB_V_DDOSC pin can be connected to the same power supply as USB_V_DDA3P3.

The USB on-chip oscillator can be permanently disabled, via tie-offs, if the USB peripheral is not being used. To permanently disable the USB oscillator, connect the USB_MXI pin to ground (V_SS) and leave the USB_MXO pin unconnected. The USB oscillator power pins (USB_V_DDOSC and USB_V_SSOSC) should also be connected to ground, as shown in Figure 5-15.

When using an external 12-MHz oscillator, the external oscillator clock signal must be connected to the USB_MXI pin and the amplitude of the oscillator clock signal must meet the V_IH requirement (see Section 5.2, Recommended Operating Conditions). The USB_MXO remains unconnected and the USB_V_SSOSC signal is connected to board ground (V_SS).

Figure 5-14 12-MHz USB Oscillator

Figure 5-15 Connections when USB Oscillator is Permanently Disabled

The crystal should be in fundamental-mode operation, and parallel resonant, with a maximum effective series resistance (ESR) specified in Table 5-12. The load capacitors, C1 and C2 are the total capacitance of the circuit board and components, excluding the IC and crystal. The load capacitor value is usually approximately twice the value of the crystal's load capacitance, CL, which is specified in the crystal manufacturer's data sheet and should be chosen such that the equation below is satisfied. All discrete components used to implement the oscillator circuit should be placed as close as possible to the associated oscillator pins (USB_MXI and USB_MXO) and to the USB_V_SSOSC pin.

Table 5-12 Input Requirements for Crystal on the 12-MHz USB Oscillator

PARAMETER	NOM	MAX	UNIT
Start-up time (from power up until oscillating at stable frequency of 12 MHz)⁽²⁾	0.100	10	ms
Oscillation frequency	12		MHz
ESR		100	Ω
Frequency stability ⁽¹⁾		±100	ppm
Maximum shunt capacitance		5	pF
Maximum crystal drive		330	μW

(1) If the USB is used, a 12-MHz, ±100-ppm crystal is recommended.

(2) The startup time is highly dependent on the ESR and the capacitive load of the crystal.

5.7.4.4 Input and Output Clocks Electrical Data and Timing

Table 5-13 Timing Requirements for CLKIN⁽¹⁾⁽²⁾ (see Figure 5-16)

NO.			CV_DD = 1.05 V			CV_DD = 1.3 V			UNIT
NO.			MIN	NOM	MAX	MIN	NOM	MAX	UNIT
1	t_c(CLKIN)	Cycle time, external clock driven on CLKIN		88.577, 83.333, or 81.380			88.577, 83.333, or 81.380		ns
2	t_w(CLKINH)	Pulse width, CLKIN high	0.466 * t_c(CLKIN)			0.466 * t_c(CLKIN)			ns
3	t_w(CLKINL)	Pulse width, CLKIN low	0.466 * t_c(CLKIN)			0.466 * t_c(CLKIN)			ns
4	t_t(CLKIN)	Transition time, CLKIN			4			4	ns

(1) The CLKIN frequency and PLL multiply factor must be chosen such that the resulting clock frequency is within the specific range for CPU operating frequency.

(2) The reference points for the rise and fall transitions are measured at V_IL MAX and V_IH MIN.

Figure 5-16 CLKIN Timing

Table 5-14 Switching Characteristics Over Recommended Operating Conditions for CLKOUT⁽¹⁾⁽²⁾
(see Figure 5-17)

NO.	PARAMETER		CV_DD = 1.05 V V_{DDA_PLL} = 1.3 V		CV_DD = 1.3 V V_{DDA_PLL} = 1.3 V		UNIT
NO.	PARAMETER		MIN	MAX	MIN	MAX	UNIT
1	t_c(CLKOUT)	Cycle time, CLKOUT	P	20	P	10	ns
2	t_w(CLKOUTH)	Pulse duration, CLKOUT high	0.466 * t_c(CLKOUT)		0.466 * t_c(CLKOUT)		ns
3	t_w(CLKOUTL)	Pulse duration, CLKOUT low	0.466 * t_c(CLKOUT)		0.466 * t_c(CLKOUT)		ns
4	t_t(CLKOUTR)	Transition time (rise), CLKOUT⁽³⁾		5		5	ns
5	t_t(CLKOUTF)	Transition time (fall), CLKOUT⁽³⁾		5		5	ns

(1) The reference points for the rise and fall transitions are measured at V_OL MAX and V_OH MIN.

(2) P = 1/SYSCLK clock frequency in nanoseconds (ns). For example, when SYSCLK frequency is 100 MHz, use P = 10 ns.

(3) Transition time is measured with the slew rate set to FAST and DV_DDIO = 1.65 V. (For more detailed information, see the Section 5.7.3.5.6, Output Slew Rate Control Register (OSRCR) [1C16h].).

Figure 5-17 CLKOUT Timing

5.7.4.5 Wake-up Events, Interrupts, and XF

The device has a number of interrupts to service the needs of its peripherals. The interrupts can be selectively enabled or disabled.

5.7.4.5.1 Interrupts Electrical Data and Timing

Table 5-15 Timing Requirements for Interrupts⁽¹⁾ (see Figure 5-18)

NO.			CV_DD = 1.05 V CV_DD = 1.3 V		UNIT
NO.			MIN	MAX	UNIT
1	t_w(INTH)	Pulse duration, interrupt high CPU active	2P		ns
2	t_w(INTL)	Pulse duration, interrupt low CPU active	2P		ns

(1) P = 1/SYSCLK clock frequency in ns. For example, when the CPU core is clocked at 100 MHz, use P = 10 ns. For example, when the CPU core is clocked at 120 MHz, use P = 8.3 ns.

Figure 5-18 External Interrupt Timings

5.7.4.5.2 Wake Up From IDLE Electrical Data and Timing

Table 5-16 Timing Requirements for Wake-Up From IDLE (see Figure 5-19)

NO.			CV_DD = 1.05 V CV_DD = 1.3 V		UNIT
NO.			MIN	MAX	UNIT
1	t_w(WKPL)	Pulse duration, WAKEUP orINTx low, SYSCLKDIS = 1	30.5		µs

Table 5-17 Switching Characteristics Over Recommended Operating Conditions For Wake-Up From IDLE⁽¹⁾⁽²⁾⁽³⁾⁽⁴⁾ (see Figure 5-19)

NO.	PARAMETER			CV_DD = 1.05 V CV_DD = 1.3 V			UNIT
NO.	PARAMETER			MIN	TYP	MAX	UNIT
2	t_d(WKEVTH-C_KLGEN)	Delay time, WAKEUP pulse complete to CPU active	IDLE3 Mode with SYSCLKDIS = 1, WAKEUP orINTx event, CLK_SEL = 1	D			ns
			IDLE3 Mode with SYSCLKDIS = 1, WAKEUP orINTx event, CLK_SEL = 0	C			ns
			IDLE2 Mode; INTx event	3P			ns

(1) D = 1/ External Clock Frequency (CLKIN).

(2) C = 1/RTCCLK= 30.5 μs. RTCCLK is the clock output of the 32.768-kHz RTC oscillator.

(3) P = 1/SYSCLK clock frequency in ns. For example, when the CPU core is clocked at 100 MHz, use P = 10 ns.

(4) Assumes the internal LDOs are used with a 0.1 μF bandgap capacitor.

A. INT[1:0] can only be used as a wake-up event for IDLE3 and IDLE2 modes.

B. RTC interrupt (internal signal) can be used as wake-up event for IDLE3 and IDLE2 modes.

C. Any unmasked interrupt can be used to exit the IDLE2 mode.

D. CLKOUT reflects either the CPU clock, SAR, USB PHY, or PLL clock dependent on the setting of the CLKOUT Clock Source Register. For this diagram, CLKOUT refers to the CPU clock.

Figure 5-19 Wake-Up From IDLE Timings ABC

5.7.4.5.3 XF Electrical Data and Timing

Table 5-18 Switching Characteristics Over Recommended Operating Conditions For XF⁽³⁾⁽²⁾
(see Figure 5-20)

NO.	PARAMETER			CV_DD = 1.05 V CV_DD = 1.3 V		UNIT
NO.	PARAMETER			MIN	MAX	UNIT
1	t_d(XF)	Delay time, CLKOUT high to XF high		0	10.2	ns

A. CLKOUT reflects either the CPU clock, SAR,USB PHY, or PLL clock dependent on the setting of the CLOCKOUT Clock Source Register. For this diagram, CLKOUT refers to the CPU clock.

Figure 5-20 XF Timings

5.7.5 Direct Memory Access (DMA) Controller

The DMA controller is used to move data among internal memory, external memory, and peripherals without intervention from the CPU and in the background of CPU operation.

The DSP includes a total of four DMA controllers. Aside from the DSP resources they can access, all four DMA controllers are identical.

The DMA controller has the following features:

Operation that is independent of the CPU.
Four channels, which allow the DMA controller to keep track of the context of four independent block transfers.
Event synchronization. DMA transfers in each channel can be made dependent on the occurrence of selected events.
An interrupt for each channel. Each channel can send an interrupt to the CPU on completion of the programmed transfer.
Ping-Pong mode allows the DMA controller to keep track of double buffering context without CPU intervention.
A dedicated clock idle domain. The four device DMA controllers can be put into a low-power state by independently turning off their input clocks.

5.7.5.1 DMA Channel Synchronization Events

The DMA controllers allow activity in their channels to be synchronized to selected events. The DSP supports 20 separate synchronization events and each channel can be tied to separate sync events independent of the other channels. Synchronization events are selected by programming the CHnEVT field in the DMAn channel event source registers (DMAnCESR1 and DMAnCESR2).

5.7.6 General-Purpose Input/Output

The GPIO peripheral provides general-purpose pins that can be configured as either inputs or outputs. When configured as an output, you can write to an internal register to control the state driven on the output pin. When configured as an input, you can detect the state of the input by reading the state of the internal register. The GPIO can also be used to send interrupts to the CPU.

The GPIO peripheral supports the following:

32 GPIO pins plus 1 general-purpose output (XF)and 4 Special-Purpose Outputs for Use With SAR — TMS320C5535 Only
- Configure up to 20 GPIO pins simultaneously
Each GPIO pin has internal pulldowns (IPDs) which can be individually disabled
Each GPIO pin can be configured to generate edge detected interrupts to the CPU on either the rising or falling edge

The device GPIO pin functions are multiplexed with various other signals. For more detailed information on what signals are multiplexed with the GPIO and how to configure them, see Section 4.2, Signal Descriptions and Section 4.3, Pin Multiplexing of this document.

5.7.6.1 GPIO Peripheral Input/Output Electrical Data and Timing

Table 5-19 Timing Requirements for GPIO Inputs⁽¹⁾ (see Figure 5-21)

NO.			CV_DD = 1.05 V CV_DD = 1.3 V		UNIT
NO.			MIN	MAX	UNIT
1	t_w(ACTIVE)	Pulse duration, GPIO input and external interrupt pulse active	2C⁽¹⁾⁽²⁾		ns
2	t_w(INACTIVE)	Pulse duration, GPIO input and external interrupt pulse inactive	C ⁽¹⁾⁽²⁾		ns

(1) The pulse width given is sufficient to get latched into the GPIO_IFR register and to generate an interrupt. However, if a user wants to have the device recognize the GPIO changes through software polling of the GPIO Data In (GPIO_DIN) register, the GPIO duration must be extended to allow the device enough time to access the GPIO register through the internal bus.

(2) C = SYSCLK period in ns. For example, when running parts at 100 MHz, use C = 10 ns.

Table 5-20 Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs
(see Figure 5-21)

NO.	PARAMETER		CV_DD = 1.05 V CV_DD = 1.3 V		UNIT
NO.	PARAMETER		MIN	MAX	UNIT
3	t_w(GPOH)	Pulse duration, GP[x] output high	3C⁽¹⁾⁽²⁾		ns
4	t_w(GPOL)	Pulse duration, GP[x] output low	3C⁽¹⁾⁽²⁾		ns

(1) This parameter value should not be used as a maximum performance specification. Actual performance of back-to-back accesses of the GPIO is dependent upon internal bus activity.

(2) C = SYSCLK period in ns. For example, when running parts at 100 MHz, use C = 10 ns.

Figure 5-21 GPIO Port Timing

5.7.6.2 GPIO Peripheral Input Latency Electrical Data and Timing

Table 5-21 Timing Requirements for GPIO Input Latency⁽¹⁾

NO.				CV_DD = 1.05 V CV_DD = 1.3 V		UNIT
NO.				MIN	MAX	UNIT
1	t_L(GPI)	Latency, GP[x] input	Polling GPIO_DIN register	5		cyc
			Polling GPIO_IFR register	7		cyc
			Interrupt Detection	8		cyc

(1) The pulse width given is sufficient to generate a CPU interrupt. However, if a user wants to have the device recognize the GP[x] input changes through software polling of the GPIO register, the GP[x] input duration must be extended to allow device enough time to access the GPIO register through the internal bus.

5.7.7 General-Purpose Timers

The device has three 32-bit software programmable timers. Each timer can be used as a general- purpose (GP) timer. Timer2 can be configured as either a GP or a Watchdog (WD) or both. General-purpose timers are typically used to provide interrupts to the CPU to schedule periodic tasks or a delayed task. A watchdog timer is used to reset the CPU in case it gets into an infinite loop. The GP timers are 32-bit timers with a 13-bit prescaler that can divide the CPU clock and uses this scaled value as a reference clock. These timers can be used to generate periodic interrupts. The watchdog timer is a 16-bit counter with a 16-bit prescaler used to provide a recovery mechanism for the device in the event of a fault condition, such as a non-exiting code loop.

The device timers support the following:

32-bit Programmable Countdown Timer
13-bit Prescaler Divider
Timer Modes:
- 32-bit General-Purpose Timer
- 32-bit Watchdog Timer (Timer2 only)
Auto Reload Option
Generates Single Interrupt to CPU (The interrupt is individually latched to determine which timer triggered the interrupt.)
Generates Active Low Pulse to the Hardware Reset (Watchdog only)
Interrupt can be used for DMA Event

5.7.8 Inter-Integrated Circuit (I2C)

The inter-integrated circuit (I2C) module provides an interface between the device and other devices compliant with Philips Semiconductors Inter-IC bus (I²C-bus™) specification version 2.1. External components attached to this 2-wire serial bus can transmit and receive 2 to 8-bit data to and from the DSP through the I2C module. The I2C port does not support CBUS compatible devices.

The I2C port supports the following features:

Compatible with Philips I2C Specification Revision 2.1 (January 2000)
Data Transfer Rate from 10 kbps to 400 kbps (Philips Fast-Mode Rate)
Noise Filter to Remove Noise 50 ns or Less
Seven- and Ten-Bit Device Addressing Modes
Master (Transmit and Receive) and Slave (Transmit and Receive) Functionality
One Read DMA Event and One Write DMA Event, which can be used by the DMA Controller
One Interrupt that can be used by the CPU
Slew-Rate Limited Open-Drain Output Buffers

The I2C module clock must be in the range from 6.7 MHz to 13.3 MHz. This is necessary for proper operation of the I2C module. With the I2C module clock in this range, the noise filters on the SDA and SCL pins suppress noise that has a duration of 50 ns or shorter. The I2C module clock is derived from the DSP clock divided by a programmable prescaler.

5.7.8.1 I2C Electrical Data and Timing

Table 5-22 Timing Requirements for I2C Timings⁽¹⁾ (see Figure 5-22)

NO.			CV_DD = 1.05 V CV_DD = 1.3 V				UNIT
			STANDARD MODE		FAST MODE
			MIN	MAX	MIN	MAX
1	t_c(SCL)	Cycle time, SCL	10		2.5		µs
2	t_{su(SCLH-SDAL)}	Setup time, SCL high before SDA low (for a repeated START condition)	4.7		0.6		µs
3	t_h(SCLL-SDAL)	Hold time, SCL low after SDA low (for a START and a repeated START condition)	4		0.6		µs
4	t_w(SCLL)	Pulse duration, SCL low	4.7		1.3		µs
5	t_w(SCLH)	Pulse duration, SCL high	4		0.6		µs
6	t_{su(SDAV-SCLH)}	Setup time, SDA valid before SCL high	250		100⁽²⁾		ns
7	t_h(SDA-SCLL)	Hold time, SDA valid after SCL low	0⁽³⁾		0⁽³⁾	0.9⁽⁴⁾	µs
8	t_w(SDAH)	Pulse duration, SDA high between STOP and START conditions	4.7		1.3		µs
9	t_r(SDA)	Rise time, SDA⁽⁶⁾		1000	20 + 0.1C_b⁽⁵⁾	300	ns
10	t_r(SCL)	Rise time, SCL⁽⁶⁾		1000	20 + 0.1C_b⁽⁵⁾	300	ns
11	t_f(SDA)	Fall time, SDA⁽⁶⁾		300	20 + 0.1C_b⁽⁵⁾	300	ns
12	t_f(SCL)	Fall time, SCL⁽⁶⁾		300	20 + 0.1C_b⁽⁵⁾	300	ns
13	t_{su(SCLH-SDAH)}	Setup time, SCL high before SDA high (for STOP condition)	4		0.6		µs
14	t_w(SP)	Pulse duration, spike (must be suppressed)			0	50	ns
15	C_b⁽⁵⁾	Capacitive load for each bus line		400		400	pF

(1) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered down. Also these pins are not 3.6 V-tolerant (their V_IH cannot go above DV_DDIO + 0.3 V).

(2) A Fast-mode I²C-bus™ device can be used in a Standard-mode I²C-bus system, but the requirement t_su(SDA-SCLH)≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line t_r max + t_su(SDA-SCLH)= 1000 + 250 = 1250 ns (according to the Standard-mode I²C-Bus Specification) before the SCL line is released.

(3) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V_IHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL.

(4) The maximum t_h(SDA-SCLL) has only to be met if the device does not stretch the low period [t_w(SCLL)] of the SCL signal.

(5) C_b = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.

(6) The rise and fall times are measured at 30% and 70% of DV_DDIO. The fall time is only slightly influenced by the external bus load (C_b) and external pullup resistor. However, the rise time (t_r) is mainly determined by the bus load capacitance and the value of the pullup resistor. The pullup resistor must be selected to meet the I2C rise and fall time values specified.

Figure 5-22 I2C Receive Timings

Table 5-23 Switching Characteristics for I2C Timings⁽¹⁾ (see Figure 5-23)

NO.	PARAMETER		CV_DD = 1.05 V CV_DD = 1.3 V				UNIT
			STANDARD MODE		FAST MODE
			MIN	MAX	MIN	MAX
16	t_c(SCL)	Cycle time, SCL	10		2.5		µs
17	t_d(SCLH-SDAL)	Delay time, SCL high to SDA low (for a repeated START condition)	4.7		0.6		µs
18	t_d(SDAL-SCLL)	Delay time, SDA low to SCL low (for a START and a repeated START condition)	4		0.6		µs
19	t_w(SCLL)	Pulse duration, SCL low	4.7		1.3		µs
20	t_w(SCLH)	Pulse duration, SCL high	4		0.6		µs
21	t_d(SDAV-SCLH)	Delay time, SDA valid to SCL high	250		100		ns
22	t_v(SCLL-SDAV)	Valid time, SDA valid after SCL low	0		0	0.9	µs
23	t_w(SDAH)	Pulse duration, SDA high between STOP and START conditions	4.7		1.3		µs
24	t_r(SDA)	Rise time, SDA⁽²⁾		1000	20 + 0.1C_b⁽¹⁾	300	ns
25	t_r(SCL)	Rise time, SCL⁽²⁾		1000	20 + 0.1C_b⁽¹⁾	300	ns
26	t_f(SDA)	Fall time, SDA⁽²⁾		300	20 + 0.1C_b⁽¹⁾	300	ns
27	t_f(SCL)	Fall time, SCL⁽²⁾		300	20 + 0.1C_b⁽¹⁾	300	ns
28	t_d(SCLH-SDAH)	Delay time, SCL high to SDA high (for STOP condition)	4		0.6		µs
29	C_p	Capacitance for each I2C pin		10		10	pF

(1) C_b = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.

(2) The rise and fall times are measured at 30% and 70% of DV_DDIO. The fall time is only slightly influenced by the external bus load (C_b) and external pullup resistor. However, the rise time (t_r) is mainly determined by the bus load capacitance and the value of the pullup resistor. The pullup resistor must be selected to meet the I2C rise and fall time values specified.

Figure 5-23 I2C Transmit Timings

5.7.9 Inter-IC Sound (I2S)

The device I2S peripherals allow serial transfer of full-duplex streaming data, usually audio data, between the device and an external I2S peripheral device such as an audio codec.

The device supports 4 independent dual-channel I2S peripherals, each with the following features:

Full-duplex (transmit and receive) dual-channel communication
Double buffered data registers that allow for continuous data streaming
I2S/Left-justified and DSP data format with a data delay of 1 or 2 bits
Data word-lengths of 8, 10, 12, 14, 16, 18, 20, 24, or 32 bits
Ability to sign-extend received data samples for easy use in signal processing algorithms
Programmable polarity for both frame synchronization and bit clocks
Stereo (in I2S/Left-justified or DSP data formats) or mono (in DSP data format) mode
Detection of over-run, under-run, and frame-sync error conditions

5.7.9.1 I2S Electrical Data and Timing

Table 5-24 Timing Requirements for I2S [I/O = 3.3 V, 2.75 V, and 2.5 V]⁽¹⁾ (see Figure 5-24)

NO.			MASTER				SLAVE				UNIT
			CV_DD = 1.05 V		CV_DD = 1.3 V		CV_DD = 1.05 V		CV_DD = 1.3 V
			MIN	MAX	MIN	MAX	MIN	MAX	MIN	MAX
1	t_c(CLK)	Cycle time, I2S_CLK	40 or 2P⁽¹⁾⁽²⁾		40 or 2P⁽¹⁾⁽²⁾		40 or 2P⁽¹⁾⁽²⁾		40 or 2P⁽¹⁾⁽²⁾		ns
2	t_w(CLKH)	Pulse duration, I2S_CLK high	20		20		20		20		ns
3	t_w(CLKL)	Pulse duration, I2S_CLK low	20		20		20		20		ns
7	t_su(RXV-CLKH)	Setup time, I2S_RX valid before I2S CLK high (CLKPOL = 0)	5		5		5		5		ns
7	t_su(RXV-CLKL)	Setup time, I2S_RX valid before I2S_CLK low (CLKPOL = 1)	5		5		5		5		ns
8	t_h(CLKH-RXV)	Hold time, I2S_RX valid after I2S_CLK high (CLKPOL = 0)	3		3		3		3		ns
8	t_h(CLKL-RXV)	Hold time, I2S_RX valid after I2S_CLK low (CLKPOL = 1)	3		3		3		3		ns
9	t_su(FSV-CLKH)	Setup time, I2S_FS valid before I2S_CLK high (CLKPOL = 0)	–		–		15		15		ns
9	t_su(FSV-CLKL)	Setup time, I2S_FS valid before I2S_CLK low (CLKPOL = 1)	–		–		15		15		ns
10	t_h(CLKH-FSV)	Hold time, I2S_FS valid after I2S_CLK high (CLKPOL = 0)	–		–		t_w(CLKH) + 0.6⁽³⁾		t_w(CLKH) + 0.6⁽³⁾		ns
10	t_h(CLKL-FSV)	Hold time, I2S_FS valid after I2S_CLK low (CLKPOL = 1)	–		–		t_w(CLKL) + 0.6⁽³⁾		t_w(CLKL) + 0.6⁽³⁾		ns

(1) P = SYSCLK period in ns. For example, when the CPU core is clocked at 100 MHz, use P = 10 ns.

(2) Use whichever value is greater.

(3) In Slave Mode, I2S_FS is required to be latched on both edges of I2S input clock (I2S_CLK).

Table 5-25 Timing Requirements for I2S
[I/O = 1.8 V]⁽¹⁾ (see Figure 5-24)

NO.			MASTER				SLAVE				UNIT
			CV_DD = 1.05 V		CV_DD = 1.3 V		CV_DD = 1.05 V		CV_DD = 1.3 V
			MIN	MAX	MIN	MAX	MIN	MAX	MIN	MAX
1	t_c(CLK)	Cycle time, I2S_CLK	50 or 2P⁽¹⁾⁽²⁾		40 or 2P⁽¹⁾⁽²⁾		50 or 2P⁽¹⁾⁽²⁾		40 or 2P⁽¹⁾⁽²⁾		ns
2	t_w(CLKH)	Pulse duration, I2S_CLK high	25		20		25		20		ns
3	t_w(CLKL)	Pulse duration, I2S_CLK low	25		20		25		20		ns
7	t_su(RXV-CLKH)	Setup time, I2S_RX valid before I2S CLK high (CLKPOL = 0)	5		5		5		5		ns
7	t_su(RXV-CLKL)	Setup time, I2S_RX valid before I2S_CLK low (CLKPOL = 1)	5		5		5		5		ns
8	t_h(CLKH-RXV)	Hold time, I2S_RX valid after I2S_CLK high (CLKPOL = 0)	3		3		3		3		ns
8	t_h(CLKL-RXV)	Hold time, I2S_RX valid after I2S_CLK low (CLKPOL = 1)	3		3		3		3		ns
9	t_su(FSV-CLKH)	Setup time, I2S_FS valid before I2S_CLK high (CLKPOL = 0)	–		–		15		15		ns
9	t_su(FSV-CLKL)	Setup time, I2S_FS valid before I2S_CLK low (CLKPOL = 1)	–		–		15		15		ns
10	t_h(CLKH-FSV)	Hold time, I2S_FS valid after I2S_CLK high (CLKPOL = 0)	–		–		t_w(CLKH) + 0.6⁽³⁾		t_w(CLKH) + 0.6⁽³⁾		ns
10	t_h(CLKL-FSV)	Hold time, I2S_FS valid after I2S_CLK low (CLKPOL = 1)	–		–		t_w(CLKL) + 0.6⁽³⁾		t_w(CLKL) + 0.6⁽³⁾		ns

(1) P = SYSCLK period in ns. For example, when the CPU core is clocked at 100 MHz, use P = 10 ns.

(2) Use whichever value is greater.

(3) In Slave Mode, I2S_FS is required to be latched on both edges of I2S input clock (I2S_CLK).

Table 5-26 Switching Characteristics Over Recommended Operating Conditions for I2S Output
[I/O = 3.3 V, 2.75 V, or 2.5 V] (see Figure 5-24)

NO.	PARAMETER		MASTER				SLAVE				UNIT
			CV_DD = 1.05 V		CV_DD = 1.3 V		CV_DD = 1.05 V		CV_DD = 1.3 V
			MIN	MAX	MIN	MAX	MIN	MAX	MIN	MAX
1	t_c(CLK)	Cycle time, I2S_CLK	40 or 2P⁽¹⁾⁽²⁾		40 or 2P⁽¹⁾⁽²⁾		40 or 2P⁽¹⁾⁽²⁾		40 or 2P⁽¹⁾⁽²⁾		ns
2	t_w(CLKH)	Pulse duration, I2S_CLK high (CLKPOL = 0)	20		20		20		20		ns
2	t_w(CLKL)	Pulse duration, I2S_CLK low (CLKPOL = 1)	20		20		20		20		ns
3	t_w(CLKL)	Pulse duration, I2S_CLK low (CLKPOL = 0)	20		20		20		20		ns
3	t_w(CLKH)	Pulse duration, I2S_CLK high (CLKPOL = 1)	20		20		20		20		ns
4	t_{dmax(CLKL-DXV)}	Output Delay time, I2S_CLK low to I2S_DX valid (CLKPOL = 0)	0	15	0	14	0	15	0	15	ns
4	t_{dmax(CLKH-DXV)}	Output Delay time, I2S_CLK high to I2S_DX valid (CLKPOL = 1)	0	15	0	14	0	15	0	15	ns
5	t_{dmax(CLKL-FSV)}	Delay time, I2S_CLK low to I2S_FS valid (CLKPOL = 0)	-1.1	14	-1.1	14		–		–	ns
5	t_{dmax(CLKH-FSV)}	Delay time, I2S_CLK high to I2S_FS valid (CLKPOL = 1)	-1.1	14	-1.1	14		–		–	ns

(1) P = SYSCLK period in ns. For example, when the CPU core is clocked at 100 MHz, use P = 10 ns.

(2) Use whichever value is greater.

Table 5-27 Switching Characteristics Over Recommended Operating Conditions for I2S Output
[I/O = 1.8 V] (see Figure 5-24)

NO.	PARAMETER		MASTER				SLAVE				UNIT
			CV_DD = 1.05 V		CV_DD = 1.3 V		CV_DD = 1.05 V		CV_DD = 1.3 V
			MIN	MAX	MIN	MAX	MIN	MAX	MIN	MAX
1	t_c(CLK)	Cycle time, I2S_CLK	50 or 2P⁽¹⁾⁽²⁾		40 or 2P⁽¹⁾⁽²⁾		50 or 2P⁽¹⁾⁽²⁾		40 or 2P⁽¹⁾⁽²⁾		ns
2	t_w(CLKH)	Pulse duration, I2S_CLK high (CLKPOL = 0)	25		20		25		20		ns
2	t_w(CLKL)	Pulse duration, I2S_CLK low (CLKPOL = 1)	25		20		25		20		ns
3	t_w(CLKL)	Pulse duration, I2S_CLK low (CLKPOL = 0)	25		20		25		20		ns
3	t_w(CLKH)	Pulse duration, I2S_CLK high (CLKPOL = 1)	25		20		25		20		ns
4	t_{dmax(CLKL-DXV)}	Output Delay time, I2S_CLK low to I2S_DX valid (CLKPOL = 0)	0	19	0	14	0	19	0	16.5	ns
4	t_{dmax(CLKH-DXV)}	Output Delay time, I2S_CLK high to I2S_DX valid (CLKPOL = 1)	0	19	0	14	0	19	0	16.5	ns
5	t_{dmax(CLKL-FSV)}	Delay time, I2S_CLK low to I2S_FS valid (CLKPOL = 0)	-1.1	14	-1.1	14		–		–	ns
5	t_{dmax(CLKH-FSV)}	Delay time, I2S_CLK high to I2S_FS valid (CLKPOL = 1)	-1.1	14	-1.1	14		–		–	ns

(1) P = SYSCLK period in ns. For example, when the CPU core is clocked at 100 MHz, use P = 10 ns.

(2) Use whichever value is greater.

Figure 5-24 I2S Input and Output Timings

5.7.10 Liquid Crystal Display Controller (LCDC) — C5535 Only

The device includes a LCD Interface Display Driver (LIDD) controller.

The LIDD Controller supports the asynchronous LCD interface and has the following features:

Provides full-timing programmability of control signals and output data

Note: Raster mode is not supported on this device.

The LCD controller is responsible for generating the correct external timing. The DMA engine provides a constant flow of data from the frame buffer to the external LCD panel via the LIDD controller. In addition, CPU access is provided to read and write registers.

Because the LCD Controller is supported on only TMS320C5535, the LCD Controller clock gate control bit in PCGCR2 must be disabled for a lower operating power on TMS320C5534, C5533, and C5532. For more information, see TMS320C5535/34/33/32 Ultra-Low Power DSP Technical Reference Manual (literature number SPRUH87).

5.7.10.1 LCDC Electrical Data and Timing

Table 5-28 Timing Requirements for LCD LIDD Mode⁽¹⁾ (see Figure 5-25 through Figure 5-32)

NO.			CV_DD = 1.05 V		CV_DD = 1.3 V		UNIT
NO.			MIN	MAX	MIN	MAX	UNIT
16	t_{su(LCD_D-CLK)}	Setup time, LCD_D[15:0] valid before LCD_CLK rising edge	27		42		ns
17	t_{h(CLK-LCD_D)}	Hold time, LCD_D[15:0] valid after LCD_CLK rising edge	0		0		ns

(1) Over operating free-air temperature range (unless otherwise noted)

Table 5-29 Switching Characteristics Over Recommended Operating Conditions for LCD LIDD Mode (see Figure 5-25 through Figure 5-32)

NO.	PARAMETER		CV_DD = 1.05 V		CV_DD = 1.3 V		UNIT
NO.	PARAMETER		MIN	MAX	MIN	MAX	UNIT
4	t_{d(LCD_D_V)}	Delay time, LCD_CLK rising edge to LCD_D[15:0] valid (write)		5		7	ns
5	t_{d(LCD_D_I)}	Delay time, LCD_CLK rising edge to LCD_D[15:0] invalid (write)	-6		-6		ns
6	t_{d(LCD_E_A)}	Delay time, LCD_CLK rising edge to LCD_CSx_Ex low		5		7	ns
7	t_{d(LCD_E_I)}	Delay time, LCD_CLKrising edge to LCD_CSx_Ex high	-6		-6		ns
8	t_{d(LCD_A_A)}	Delay time, LCD_CLKrising edge to LCD_RS low		5		7	ns
9	t_{d(LCD_A_I)}	Delay time, LCD_CLK rising edge to LCD_RS high	-6		-6		ns
10	t_{d(LCD_W_A)}	Delay time, LCD_CLK rising edge to LCD_RW_WRB low		5		7	ns
11	t_{d(LCD_W_I)}	Delay time, LCD_CLK rising edge to LCD_RW_WRB high	-6		-6		ns
12	t_{d(LCD_STRB_A)}	Delay time, LCD_CLK rising edge to LCD_EN_RDB high		5		7	ns
13	t_{d(LCD_STRB_I)}	Delay time, LCD_CLK rising edge to LCD_EN_RDB low	-6		-6		ns
14	t_{d(LCD_D_Z)}	Delay time, LCD_CLK rising edge to LCD_D[15:0] in 3-state		5		7	ns
15	t_{d(Z_LCD_D)}	Delay time, LCD_CLK rising edge to LCD_D[15:0] valid from 3-state	-6		-6		ns

Figure 5-25 Character Display HD44780 Write

Figure 5-26 Character Display HD44780 Read

Figure 5-27 Micro-Interface Graphic Display 6800 Write

Figure 5-28 Micro-Interface Graphic Display 6800 Read

Figure 5-29 Micro-Interface Graphic Display 6800 Status

Figure 5-30 Micro-Interface Graphic Display 8080 Write

Figure 5-31 Micro-Interface Graphic Display 8080 Read

Figure 5-32 Micro-Interface Graphic Display 8080 Status

5.7.11 Real-Time Clock (RTC)

The device includes a Real-Time Clock (RTC) with its own separated power supply and isolation circuits. The separate supply and isolation circuits allow the RTC to run with the least possible power consumption, called RTC-only mode. The RTC-only mode requires CV_DDRTC, LDOI, and DV_DDRTC power domains to be powered, but other power domains can be shut off. See Section 5.7.11.1, RTC-Only Mode for details. All RTC registers are preserved (except for RTC Control and RTC Update Registers) and the counter continues to operate when the device is powered off.

The RTC also has the capability to wake up the device from idle states via alarms, periodic interrupts, or an external WAKEUP input. Additionally, the RTC is able to output an alarm or periodic interrupt on the WAKEUP pin to cause external power management to re-enable power to the DSP Core and I/O.Note: The RTC Core (CV_DDRTC) must be properly powered by an external power source even though RTC is not used. None of the on-chip LDOs can power CV_DDRTC.

The device RTC provides the following features:

100-year calendar up to year 2099.
Counts seconds, minutes, hours, day of the week, date, month, and year with leap year compensation
Millisecond time correction
Binary-coded-decimal (BCD) representation of time, calendar, and alarm
24-hour clock mode
Second, minute, hour, day, or week alarm interrupt
Periodic interrupt: every millisecond, second, minute, hour, or day
Alarm interrupt: precise time of day
Single interrupt to the DSP CPU
32.768-kHz crystal oscillator with frequency calibration

Control of the RTC is maintained through a set of I/O memory mapped registers (see Table 6-15). Note that any write to these registers will be synchronized to the RTC 32.768-kHz clock; thus, the CPU must run at least 3X faster than the RTC. Writes to these registers will not be evident until the next two 32.768-kHz clock cycles later. Furthermore, if the RTC Oscillator is disabled, no RTC register can be written to.

The RTC has its own power-on-reset (POR) circuit which resets the registers in the RTC core domain when power is first applied to the CV_DDRTC power pin. The RTC flops are not reset by the device's RESET pin nor the digital core's POR (powergood signal).

The scratch registers in the RTC can be used to take advantage of this unique reset domain to keep track of when the DSP boots and whether the RTC time registers have already been initialized to the current clock time or whether the software needs to go into a routine to prompt the user to set the time and date.

5.7.11.1 RTC-Only Mode

The lowest power consumption can be achieved by using RTC-only mode. There are hardware and software requirements to use RTC-only mode.

Hardware Requirements:

The DSP_LDO_EN pin must be tied to GND or pulled down to GND.
The RTC Core (CV_DDRTC), RTC I/O (DV_DDRTC), and LDO inputs (LDOI) must be always powered. CV_DDRTC must be powered using an external power source.
VDDA_ANA is recommended to be powered from the ANA_LDOO pin. (In case VDDA_ANA has to be powered externally, then VDDA_ANA must be always powered, too.)
All other power domains can be totally shut down when using RTC-only mode.
- Verify the USB oscillator is disabled according to the workaround described in
  TMS320C5535/34/33/32 Fixed-Point DSP Silicon Errata (Silicon Revision 2.2) (literature number SPRZ373).
A high pulse for a minimum of one RTC clock period (30.5 µs) to the WAKEUP pin is required to wake up the device from the RTC only mode.

Power Down Sequence:

CPU must set the LDO_PD bit or the BG_PD bit in the RTCPMGT register (See Figure 5-3). Once the LDO_PD bit or the BG_PD bit is set to 1, the DSP_LDOO will be internally shut off and it will cause the internal POR holds the internal POWERGOOD signal low, which creates isolation for RTC.
All of the device power domains can be shut down except RTC Core (CV_DDRTC), RTC I/O (DV_DDRTC), and LDO inputs (LDOI).

Wake-Up Sequence:

When waking up the device, all power domains must be turned back on before or upon applying a pulse to WAKEUP.
A pulse (≥ 30.5 µs) must be applied to the WAKEUP pin (active high). When the WAKEUP pin is asserted, the voltage on the DSP_LDOO pin will start ramping up and it is monitored by the internal POR. Until the voltage reaches to the threshold level, the internal POR will hold the internal POWERGOOD signal low, which provides isolation to RTC during transition period. Once the voltage reaches to the threshold level, the internal POR asserts the internal POWERGOOD signal (logic level high) and it resets reset of the system and disables RTC isolation and enables CPU to communicate with RTC.

5.7.12 SAR ADC (10-Bit) — C5535 Only

The device includes a 10-bit SAR ADC using a switched capacitor architecture which converts an analog input signal to a digital value at a maximum rate of 62.5-k samples per second (ksps) for use by the DSP. This SAR module supports six channels that are connected to four general purpose analog pins (GPAIN [3:0 ]) which can be used as general purpose outputs.

The device SAR supports the following features:

Up to 62.5 ksps (2-MHz clock with 32 cycles per conversion)
Single conversion and continuous back-to-back conversion modes
Interrupt driven or polling conversion or DMA event generation
Internal configurable bandgap reference voltages of 1 V or 0.8 V; or external V_ref of V_{DDA_ANA}
One 3.6-V Tolerant analog input (GPAIN0) with internal voltage division for conversion of battery voltage
Software controlled power down
Individually configurable general-purpose digital outputs

5.7.12.1 SAR ADC Electrical Data and Timing

Table 5-30 Switching Characteristics Over Recommended Operating Conditions for ADC Characteristics

NO.	PARAMETER		CV_DD = 1.3 V CV_DD = 1.05 V			UNIT
NO.	PARAMETER		MIN	TYP	MAX	UNIT
1	t_C(SCLC)	Cycle time, ADC internal conversion clock			2	MHz
3	t_d(CONV)	Delay time, ADC conversion time			32t_C(SCLC)	ns
4	S_DNL	Static differential non-linearity error (DNL measured for 9 bits)		±0.6		LSB
5	S_INL	Static integral non-linearity error		±1		LSB
6	Z_set	Zero-scale offset error (INL measured for 9 bits)			2	LSB
7	F_set	Full-scale offset error			2	LSB
8		Analog input impedance	1			MΩ
9		Signal-to-noise ratio		54		dB

5.7.13 Secure Digital (SD)

The device includes two SD controllers which are compliant with Secure Digital Part 1 Physical Layer Specification V2.0 and Secure Digital Input Output (SDIO) V2.0 and eMMC V4.3 specifications. The SD card controller supports these industry standards and assumes the reader is familiar with these standards.

Each SD controller in the device has the following features:

Embedded Multimedia Card and Secure Digital (eMMC, SD, HCSD, and HSSD) protocol support
Programmable clock frequency
512-bit read and write FIFO to lower system overhead
Slave DMA transfer capability

The SD card controller transfers data between the CPU and DMA controller on one side and the SD card on the other side. The CPU and DMA controller can read and write the data in the card by accessing the registers in the SD controller.

The SD controller on this device, does not support the SPI mode of operation.

5.7.13.1 SD Electrical Data and Timing

Table 5-31 Timing Requirements for SD (see Figure 5-33 and Figure 5-36)

NO.			CV_DD = 1.3 V		CV_DD = 1.05 V		UNIT
			FAST MODE		STD MODE
			MIN	MAX	MIN	MAX
1	t_{su(CMDV-CLKH)}	Setup time, SDx_CMD data input valid before SDx_CLK high	3		3		ns
2	t_h(CLKH-CMDV)	Hold time, SDx_CMD data input valid after SDx_CLK high	3		3		ns
3	t_{su(DATV-CLKH)}	Setup time, SD_Dx data input valid before SDx_CLK high	3		3		ns
4	t_h(CLKH-DATV)	Hold time, SD_Dx data input valid after SDx_CLK high	3		3		ns

Table 5-32 Switching Characteristics Over Recommended Operating Conditions for SD Output⁽²⁾ (see Figure 5-33 and Figure 5-36)

NO.	PARAMETER		CV_DD = 1.3 V		CV_DD = 1.05 V		UNIT
			FAST MODE		STD MODE
			MIN	MAX	MIN	MAX
7	f_(CLK)	Operating frequency, SDx_CLK	0	50⁽¹⁾	0	25⁽¹⁾	MHz
8	f_{(CLK_ID)}	Identification mode frequency, SDx_CLK	0	400	0	400	kHz
9	t_w(CLKL)	Pulse width, SDx_CLK low	7		10		ns
10	t_w(CLKH)	Pulse width, SDx_CLK high	7		10		ns
11	t_r(CLK)	Rise time, SDx_CLK		3		3	ns
12	t_f(CLK)	Fall time, SDx_CLK		3		3	ns
13	t_{d(MDCLKL-CMDIV)}	Delay time, SDx_CLK low to SD_CMD data output invalid	-4		-4.1		ns
14	t_{d(MDCLKL-CMDV)}	Delay time, SDx_CLK low to SD_CMD data output valid		4		5.1	ns
15	t_{d(MDCLKL-DATIV)}	Delay time, SDx_CLK low to SD_Dx data output invalid	-4		-4.1		ns
16	t_{d(MDCLKL-DATV)}	Delay time, SDx_CLK low to SD_Dx data output valid		4		5.1	ns

(1) Use this value or SYS_CLK/2 whichever is smaller.

(2) For SD, the parametric values are measured at DV_DDIO = 3.3 V and 2.75 V.

Figure 5-33 SD Host Command Write Timing

Figure 5-34 SD Card Response Timing

Figure 5-35 SD Host Write Timing

Figure 5-36 SD Data Write Timing

5.7.14 Serial Port Interface (SPI)

The device serial port interface (SPI) is a high-speed synchronous serial input/output port that allows a serial bit stream of programmed length (1 to 32 bits) to be shifted into and out of the device at a programmed bit-transfer rate. The SPI supports multi-chip operation of up to four SPI slave devices. The SPI can operate as a master device only, slave mode is not supported.Note: The SPI is not supported by the device DMA controller, so DMA cannot be used in transferring data between the SPI and the on-chip RAM.

The SPI is normally used for communication between the DSP and external peripherals. Typical applications include an interface to external I/O or peripheral expansion via devices such as shift registers, display drivers, SPI EEPROMs, and analog-to-digital converters.

The SPI has the following features:

Programmable divider for serial data clock generation
Four pin interface (SPI_CLK, SPI_CSn, SPI_RX, and SPI_TX)
Programmable data length (1 to 32 bits)
4 external chip select signals
Programmable transfer or frame size (1 to 4096 characters)
Optional interrupt generation on character completion
Programmable SPI_CSn to SPI_TX delay from 0 to 3 SPI_CLK cycles
Programmable signal polarities
Programmable active clock edge
Internal loopback mode for testing

5.7.14.1 SPI Electrical Data and Timing

Table 5-33 Timing Requirements for SPI Inputs (see Figure 5-37 through Figure 5-40)

NO.			CV_DD = 1.05 V		CV_DD = 1.3 V		UNIT
NO.			MIN	MAX	MIN	MAX	UNIT
4	t_C(SCLK)	Cycle time, SPI_CLK	66.4 or 4P⁽¹⁾⁽²⁾		40 or 4P⁽¹⁾⁽²⁾		ns
5	t_w(SCLKH)	Pulse duration, SPI_CLK high	30		19		ns
6	t_w(SCLKL)	Pulse duration, SPI_CLK low	30		19		ns
7	t_{su(SRXV-SCLK)}	Setup time, SPI_RX valid before SPI_CLK high, SPI Mode 0	16.1		13.9		ns
		Setup time, SPI_RX valid before SPI_CLK low, SPI Mode 1	16.1		13.9		ns
		Setup time, SPI_RX valid before SPI_CLK high, SPI Mode 2	16.1		13.9		ns
		Setup time, SPI_RX valid before SPI_CLK high, SPI Mode 3	16.1		13.9		ns
8	t_h(SCLK-SRXV)	Hold time, SPI_RX valid after SPI_CLK high, SPI Mode 0	0		0		ns
		Hold time, SPI_RX valid after SPI_CLK low, SPI Mode 1	0		0		ns
		Hold time, SPI_RX valid after SPI_CLK low, SPI Mode 2	0		0		ns
		Hold time, SPI_RX valid after SPI_CLK high, SPI Mode 3	0		0		ns

(1) P = SYSCLK period in ns. For example, when the CPU core is clocked at 100 MHz, use P = 10 ns.

(2) Use whichever value is greater.

Table 5-34 Switching Characteristics Over Recommended Operating Conditions for SPI Outputs
(see Figure 5-37 through Figure 5-40)

NO.	PARAMETER		CV_DD = 1.05 V		CV_DD = 1.3 V		UNIT
NO.	PARAMETER		MIN	MAX	MIN	MAX	UNIT
1	t_d(SCLK-STXV)	Delay time, SPI_CLK low to SPI_TX valid, SPI Mode 0	-4.2	8.9	-4.9	5.3	ns
		Delay time, SPI_CLK high to SPI_TX valid, SPI Mode 1	-4.2	8.9	-4.9	5.3	ns
		Delay time, SPI_CLK high to SPI_TX valid, SPI Mode 2	-4.2	8.9	-4.9	5.3	ns
		Delay time, SPI_CLK low to SPI_TX valid, SPI Mode 3	-4.2	8.9	-4.9	5.3	ns
2	t_{d(SPICS-SCLK)}	Delay time, SPI_CS active to SPI_CLK active		t_C- 8 + D⁽¹⁾		t_C- 8 + D⁽¹⁾	ns
3	t_{oh(SCLKI-SPICSI)}	Output hold time, SPI_CS inactive to SPI_CLK inactive	0.5t_C- 2.2		0.5t_C- 2.2		ns

(1) D is the programable data delay in ns. Data delay can be programmed to 0, 1, 2, or 3 SPICLK clock cycles.

A. Character length is programmable between 1 and 32 bits; 8-bit character length shown.

B. Polarity of SPI_CSn is configurable, active-low polarity is shown.

Figure 5-37 SPI Mode 0 Transfer (CKPn = 0, CKPHn = 0)

A. Character length is programmable between 1 and 32 bits; 8-bit character length shown.

B. Polarity of SPI_CSn is configurable, active-low polarity is shown.

Figure 5-38 SPI Mode 1 Transfer (CKPn = 0, CKPHn = 1)

A. Character length is programmable between 1 and 32 bits; 8-bit character length shown.

B. Polarity of SPI_CSn is configurable, active-low polarity is shown.

Figure 5-39 SPI Mode 2 Transfer (CKPn = 1, CKPHn = 0)

A. Character length is programmable between 1 and 32 bits; 8-bit character length shown.

B. Polarity of SPI_CSn is configurable, active-low polarity is shown.

Figure 5-40 SPI Mode 3 Transfer (CKPn = 1, CKPHn = 1)

5.7.15 Universal Asynchronous Receiver/Transmitter (UART)

The UART performs serial-to-parallel conversions on data received from an external peripheral device and parallel-to-serial conversions on data transmitted to an external peripheral device via a serial bus.

The device has one UART peripheral with the following features:

Programmable baud rates (frequency pre-scale values from 1 to 65535)
Fully programmable serial interface characteristics:
- 5, 6, 7, or 8-bit characters
- Even, odd, or no PARITY bit generation and detection
- 1, 1.5, or 2 STOP bit generation
16-byte depth transmitter and receiver FIFOs:
- The UART can be operated with or without the FIFOs
- 1, 4, 8, or 14 byte selectable receiver FIFO trigger level for autoflow control and DMA
DMA signaling capability for both received and transmitted data
CPU interrupt capability for both received and transmitted data
False START bit detection
Line break generation and detection
Internal diagnostic capabilities:
- Loopback controls for communications link fault isolation
- Break, parity, overrun, and framing error simulation
Programmable autoflow control using CTS and RTS signals

5.7.15.1 UART Electrical Data and Timing [Receive and Transmit]

Table 5-35 Timing Requirements for UART Receive⁽¹⁾⁽²⁾ (see Figure 5-41)

NO.			CV_DD = 1.05 V		CV_DD = 1.3 V		UNIT
NO.			MIN	MAX	MIN	MAX	UNIT
4	t_w(URXDB)	Pulse duration, receive data bit (UART_RXD) [15/30 pF]	U - 3.5	U + 3	U - 3.5	U + 3	ns
5	t_w(URXSB)	Pulse duration, receive start bit [15/30 pF]	U - 3.5	U + 3	U - 3.5	U + 3	ns

(1) U = UART baud time = 1/programmed baud rate.

(2) Based on a maximum CPU frequency of 50 MHz.

Table 5-36 Switching Characteristics Over Recommended Operating Conditions for UART Transmit⁽¹⁾⁽²⁾
(see Figure 5-41)

NO.	PARAMETER		CV_DD = 1.05 V		CV_DD = 1.3V		UNIT
NO.	PARAMETER		MIN	MAX	MIN	MAX	UNIT
1	f_(baud)	Maximum programmable bit rate		3.75		6.25	MHz
2	t_w(UTXDB)	Pulse duration, transmit data bit (UART_TXD) [15/30 pF]	U - 3.5	U + 4	U - 3.5	U + 4	ns
3	t_w(UTXSB)	Pulse duration, transmit start bit [15/30 pF]	U - 3.5	U + 4	U - 3.5	U + 4	ns

(1) U = UART baud time = 1/programmed baud rate.

(2) Based on a maximum CPU frequency of 50 MHz.

Figure 5-41 UART Transmit and Receive Timing

5.7.16 Universal Serial Bus (USB) 2.0 Controller — Does Not Apply to C5532

The device USB2.0 peripheral supports the following features:

USB2.0 peripheral at speeds high-speed (480Mb/s) and full-speed (12Mb/s)
All transfer modes (control, bulk, interrupt, and isochronous asynchronous mode)
4 Transmit (TX) and 4 Receive (RX) Endpoints in addition to Control Endpoint 0
FIFO RAM
- 4K endpoint
- Programmable size
Integrated USB2.0 High Speed PHY
RNDIS mode for accelerating RNDIS type protocols using short packet termination over USB

The USB2.0 peripheral on this device, does not support:

Host Mode (Peripheral and Device Modes supported only)
On-Chip Charge Pump
On-the-Go (OTG) Mode

5.7.16.1 USB 2.0 Electrical Data and Timing

Table 5-37 Switching Characteristics Over Recommended Operating Conditions for USB 2.0 (see Figure 5-42)

NO.	PARAMETER		CV_DD = 1.05 V CV_DD = 1.3 V				UNIT
			FULL SPEED 12 Mbps		HIGH SPEED 480 Mbps⁽³⁾
			MIN	MAX	MIN	MAX
1	t_r(D)	Rise time, USB_DP and USB_DM signals⁽⁴⁾	4	20	0.5		ns
2	t_f(D)	Fall time, USB_DP and USB_DM signals⁽⁴⁾	4	20	0.5		ns
3	t_rfM	Rise and Fall time, matching⁽¹⁾	90	111	–	–	%
4	V_CRS	Output signal cross-over voltage⁽⁴⁾	1.3	2	–	–	V
7	t_w(EOPT)	Pulse duration, EOP transmitter⁽²⁾	160	175	–	–	ns
8	t_w(EOPR)	Pulse duration, EOP receiver⁽²⁾	82		–		ns
9	t_(DRATE)	Data Rate		12		480	Mb/s
10	Z_DRV	Driver Output Resistance	40.5	49.5	40.5	49.5	Ω
11	Z_INP	Receiver Input Impedance	100k		-	-	Ω

(1) t_RFM = (t_r/t_f) x 100. [Excluding the first transaction from the Idle state.]

(2) Must accept as valid EOP

(3) For more detailed information, see the Universal Serial Bus Specification, Revision 2.0, Chapter 7.

(4) Full Speed and High Speed C_L = 50 pF

Figure 5-42 USB2.0 Integrated Transceiver Interface Timing

5.7.17 Emulation and Debug

5.7.17.1 Debugging Considerations

5.7.17.1.1 Pullup and Pulldown Resistors

Proper board design should ensure that input pins to the device DSP always be at a valid logic level and not floating. This may be achieved via pullup and pulldown resistors. The DSP features internal pullup (IPU) and internal pulldown (IPD) resistors on many pins, including all GPIO pins, to eliminate the need, unless otherwise noted, for external pullup and pulldown resistors.

An external pullup and pulldown resistor may need to be used in the following situations:

Configuration Pins: An external pullup and pulldown resistor is recommended to set the desired value or state (see the configuration pins listed in Table 5-8, Default Functions Affected by Device Configuration Pins). Note that some configuration pins must be connected directly to ground or to a specific supply voltage.
Other Input Pins: If the IPU and IPD does not match the desired value or state, use an external pullup and pulldown resistor to pull the signal to the opposite rail.

For the configuration pins (listed in Table 5-8, Default Functions Affected by Device Configuration Pins), if they are both routed out and high-impedance state (not driven), it is strongly recommended that an external pullup and pulldown resistor be implemented. In addition, applying external pullup and pulldown resistors on the configuration pins adds convenience to the user in debugging and flexibility in switching operating modes.

When an external pullup or pulldown resistor is used on a pin, the pin’s internal pullup or pulldown resistor must be disabled through the Pullup and Pulldown Inhibit Registers (PDINHIBR1, 2, and 3) [1C17h, 1C18h, and 1C19h, respectively] to minimize power consumption.

Tips for choosing an external pullup and pulldown resistor:

Consider the total amount of current that may pass through the pullup or pulldown resistor. Make sure to include the leakage currents of all the devices connected to the net, as well as any internal pullup or pulldown (IPU and IPD) resistors.
Decide a target value for the net. For a pulldown resistor, this should be below the lowest V_IL level of all inputs connected to the net. For a pullup resistor, this should be above the highest V_IH level of all inputs on the net. A reasonable choice would be to target the V_OL or V_OH levels for the logic family of the limiting device; which, by definition, have margin to the V_IL and V_IH levels.
Select a pullup and pulldown resistor with the largest possible value; but, which can still ensure that the net will reach the target pulled value when maximum current from all devices on the net is flowing through the resistor. The current to be considered includes leakage current plus, any other internal and external pullup and pulldown resistors on the net.
For bidirectional nets, there is an additional consideration which sets a lower limit on the resistance value of the external resistor. Verify that the resistance is small enough that the weakest output buffer can drive the net to the opposite logic level (including margin).
Remember to include tolerances when selecting the resistor value.
For pullup resistors, also remember to include tolerances on the DV_DDIO rail.

For most systems, a 1-kΩ resistor can be used to oppose the IPU and IPD while meeting the above criteria. Users should confirm this resistor value is correct for their specific application.

For most systems, a 20-kΩ resistor can be used to compliment the IPU and IPD on the configuration pins while meeting the above criteria. Users should confirm this resistor value is correct for their specific application.

For more detailed information on input current (I_I), and the low- and high-level input voltages (V_IL and V_IH) for the device DSP, see Section 5.3, Electrical Characteristics.

For the internal pullup and pulldown resistors for all device pins, see the peripheral and system-specific signal descriptions table in this document.

5.7.17.1.2 Bus Holders

The device has special I/O bus-holder structures to ensure pins are not left floating when CV_DD power is removed while I/O power is applied. When CV_DD is "ON", the bus-holders are disabled and the internal pullups or pulldowns, if applicable, function normally. But when CV_DD is "OFF" and the I/O supply is "ON", the bus-holders become enabled and any applicable internal pullups and pulldowns are disabled.

The bus-holders are weak drivers on the pin and, for as long as CV_DD is "OFF" and I/O power is "ON", they hold the last state on the pin. If an external device is strongly driving the device I/O pin to the opposite state then the bus-holder will flip state to match the external driver and DC current will stop.

This bus-holder feature prevents unnecessary power consumption when CV_DD is "OFF" and I/O supply is "ON". For example, current caused by undriven pins (input buffer oscillation) or DC current flowing through pullups or pulldowns.

If external pullup or pulldown resistors are implemented, then care must be taken that those pullup and pulldown resistors can exceed the internal bus-holder's max current and thereby cause the bus-holder to flip state to match the state of the external pullup or pulldown. Otherwise, DC current will flow unnecessarily. When CV_DD power is applied, the bus holders are disabled (for further details on bus holders, see Section 5.7.2.5, Digital I/O Behavior When Core Power (CV_DD) is Down).

5.7.17.1.3 CLKOUT Pin

For debug purposes only, the DSP includes a CLKOUT pin which can be used to tap different clocks within the clock generator. The SRC bits of the CLKOUT Control Source Register (CCSSR) can be used to specify the source for the CLKOUT pin.

Note: The bootloader disables the CLKOUT pin via CLKOFF bit in the ST3_55 CPU register.

For more information on the ST3_55 CPU register, see the TMS320C55x 3.0 CPU Reference Guide (literature number: SWPU073).

5.7.18 IEEE 1149.1 JTAG

The JTAG interface is used for Boundary-Scan testing and emulation of the device.

TRST should only to be deasserted when it is necessary to use a JTAG controller to debug the device or exercise the device's boundary scan functionality.

The device includes an internal pulldown (IPD) on the TRST pin to ensure that TRST will always be asserted upon power up and the device's internal emulation logic will always be properly initialized. An external pulldown is also recommended to ensure proper device operation when an emulation or boundary scan JTAG controller is not connected to the JTAG pins. JTAG controllers from Texas Instruments actively drive TRST high. However, some third-party JTAG controllers may not drive TRST high but expect the use of a pullup resistor on TRST. When using this type of JTAG controller, assert TRST to initialize the device after powerup and externally drive TRST high before attempting any emulation or boundary scan operations. The device will not operate properly if TRST is not asserted low during powerup.

5.7.18.1 JTAG Test_port Electrical Data and Timing

Table 5-38 Timing Requirements for JTAG Test Port (see Figure 5-43)

NO.			CV_DD = 1.05 V CV_DD = 1.3 V		UNIT
NO.			MIN	MAX	UNIT
2	t_c(TCK)	Cycle time, TCK	60		ns
3	t_w(TCKH)	Pulse duration, TCK high	24		ns
4	t_w(TCKL)	Pulse duration, TCK low	24		ns
5	t_{su(TDIV-TCKH)}	Setup time, TDI valid before TCK high	10		ns
6	t_{su(TMSV-TCKH)}	Setup time, TMS valid before TCK high	6		ns
7	t_h(TCKH-TDIV)	Hold time, TDI valid after TCK high	5		ns
8	t_h(TCKH-TDIV)	Hold time, TMS valid after TCK high	4		ns

Table 5-39 Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port
(see Figure 5-43)

NO.	PARAMETER		CV_DD = 1.05 V CV_DD = 1.3 V		UNIT
NO.	PARAMETER		MIN	MAX	UNIT
1	t_d(TCKL-TDOV)	Delay time, TCK low to TDO valid		30.5	ns

Figure 5-43 JTAG Test-Port Timing

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5 Specifications

5.1 Absolute Maximum Ratings

5.2 Recommended Operating Conditions

5.3 Electrical Characteristics

5.4 Handling Ratings

5.5 Thermal Characteristics

5.6 Power-On Hours

5.7 Timing and Switching Characteristics

5.7.1 Parameter Information

5.7.1.1 1.8-V, 2.5-V, 2.75-V, and 3.3-V Signal Transition Levels

5.7.1.2 3.3-V Signal Transition Rates

5.7.1.3 Timing Parameters and Board Routing Analysis

5.7.2 Power Supplies

5.7.2.1 Power Considerations for C5535 and C5534

5.7.2.1.1 LDO Configuration

5.7.2.1.1.1 LDO Inputs

5.7.2.1.1.2 LDO Outputs

5.7.2.1.1.3 LDO Control

Table 5-1 RTCPMGT Register Bit Descriptions

Table 5-2 LDOCNTL Register Bit Descriptions

Table 5-3 LDO Controls Matrix

5.7.2.2 Power Considerations for C5533

5.7.2.2.1 LDO Configuration

5.7.2.2.1.1 LDO Inputs

5.7.2.2.1.2 LDO Outputs

5.7.2.2.1.3 LDO Control

Table 5-4 RTCPMGT Register Bit Descriptions

Table 5-5 LDOCNTL Register Bit Descriptions

Table 5-6 LDO Controls Matrix

5.7.2.3 Power Considerations for C5532

5.7.2.3.1 LDO Configuration

5.7.2.3.2 LDO Inputs

5.7.2.3.3 LDO Outputs

5.7.2.4 Power-Supply Sequencing

5.7.2.5 Digital I/O Behavior When Core Power (CVDD) is Down

5.7.2.6 Power-Supply Design Considerations

5.7.2.7 Power-Supply Decoupling

5.7.2.8 LDO Input Decoupling

5.7.2.9 LDO Output Decoupling

5.7.3 Reset

5.7.3.1 Power-On Reset (POR) Circuits

5.7.3.1.1 RTC Power-On Reset (POR)

5.7.3.1.2 Main Power-On Reset (POR)

5.7.3.1.3 Reset Pin (RESET)

5.7.3.2 Pin Behavior at Reset

5.7.3.3 Reset Electrical Data and Timing

Table 5-7 Timing Requirements for Reset(1) (see Figure 5-8 and Figure 5-9)

5.7.3.4 Configurations at Reset

5.7.3.4.1 Device and Peripheral Configurations at Device Reset

Table 5-8 Default Functions Affected by Device Configuration Pins

5.7.3.5 Configurations After Reset

5.7.3.5.1 External Bus Selection Register (EBSR)

Table 5-9 EBSR Register Bit Descriptions

5.7.3.5.2 LDO Control Register [7004h]

5.7.3.5.3 USB System Control Registers (USBSCR) [1C32h]

5.7.3.5.4 Peripheral Clock Gating Control Registers (PCGCR1 and PCGCR2) [1C02h and 1C03h]

5.7.3.5.5 Pullup and Pulldown Inhibit Registers (PDINHIBR1, 2, and 3) [1C17h, 1C18h, and 1C19h]

5.7.3.5.6 Output Slew Rate Control Register (OSRCR) [1C16h]

5.7.4 Clock Specifications

5.7.4.1 Recommended Clock and Control Signal Transition Behavior

5.7.4.2 Clock Considerations

5.7.4.2.1 Clock Configurations After Device Reset

5.7.4.2.1.1 Device Clock Frequency

5.7.4.2.1.2 Peripheral Clock State

5.7.4.2.1.3 USB Oscillator Control

5.7.4.3 PLLs

5.7.4.3.1 PLL Device-Specific Information

Table 5-10 PLL Clock Frequency Ranges

5.7.4.3.2 Clock PLL Considerations With External Clock Sources

5.7.4.3.3 External Clock Input From RTC_XI, CLKIN, and USB_MXI Pins

5.7.4.3.3.1 Real-Time Clock (RTC) On-Chip Oscillator With External Crystal

Table 5-11 Input Requirements for Crystal on the 32.768-kHz RTC Oscillator

5.7.4.3.3.2 CLKIN Pin With LVCMOS-Compatible Clock Input (Optional)

5.7.4.3.3.3 USB On-Chip Oscillator With External Crystal (Optional)

Table 5-12 Input Requirements for Crystal on the 12-MHz USB Oscillator

5.7.4.4 Input and Output Clocks Electrical Data and Timing

5.7.2.5 Digital I/O Behavior When Core Power (CV_DD) is Down

Table 5-7 Timing Requirements for Reset⁽¹⁾ (see Figure 5-8 and Figure 5-9)

Table 5-13 Timing Requirements for CLKIN⁽¹⁾⁽²⁾ (see Figure 5-16)

Table 5-14 Switching Characteristics Over Recommended Operating Conditions for CLKOUT⁽¹⁾⁽²⁾
(see Figure 5-17)

Table 5-15 Timing Requirements for Interrupts⁽¹⁾ (see Figure 5-18)

Table 5-17 Switching Characteristics Over Recommended Operating Conditions For Wake-Up From IDLE⁽¹⁾⁽²⁾⁽³⁾⁽⁴⁾ (see Figure 5-19)

Table 5-18 Switching Characteristics Over Recommended Operating Conditions For XF⁽³⁾⁽²⁾
(see Figure 5-20)

Table 5-19 Timing Requirements for GPIO Inputs⁽¹⁾ (see Figure 5-21)

Table 5-20 Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs
(see Figure 5-21)

Table 5-21 Timing Requirements for GPIO Input Latency⁽¹⁾

Table 5-22 Timing Requirements for I2C Timings⁽¹⁾ (see Figure 5-22)

Table 5-23 Switching Characteristics for I2C Timings⁽¹⁾ (see Figure 5-23)

Table 5-24 Timing Requirements for I2S [I/O = 3.3 V, 2.75 V, and 2.5 V]⁽¹⁾ (see Figure 5-24)

Table 5-25 Timing Requirements for I2S
[I/O = 1.8 V]⁽¹⁾ (see Figure 5-24)

Table 5-26 Switching Characteristics Over Recommended Operating Conditions for I2S Output
[I/O = 3.3 V, 2.75 V, or 2.5 V] (see Figure 5-24)

Table 5-27 Switching Characteristics Over Recommended Operating Conditions for I2S Output
[I/O = 1.8 V] (see Figure 5-24)

Table 5-28 Timing Requirements for LCD LIDD Mode⁽¹⁾ (see Figure 5-25 through Figure 5-32)

Table 5-32 Switching Characteristics Over Recommended Operating Conditions for SD Output⁽²⁾ (see Figure 5-33 and Figure 5-36)

Table 5-34 Switching Characteristics Over Recommended Operating Conditions for SPI Outputs
(see Figure 5-37 through Figure 5-40)

Table 5-35 Timing Requirements for UART Receive⁽¹⁾⁽²⁾ (see Figure 5-41)

Table 5-36 Switching Characteristics Over Recommended Operating Conditions for UART Transmit⁽¹⁾⁽²⁾
(see Figure 5-41)

Table 5-39 Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port
(see Figure 5-43)