ZHCS277C August   2011  – April 2014 TMS320C5532 , TMS320C5533 , TMS320C5534 , TMS320C5535

PRODUCTION DATA.  

  1. 1器件概述
    1. 1.1 特性
    2. 1.2 应用
    3. 1.3 说明
    4. 1.4 功能方框图
  2. 2修订历史记录
  3. 3Device Comparison
    1. 3.1 Device Characteristics
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Signal Descriptions
      1. 4.2.1  Oscillator and PLL
      2. 4.2.2  Real-Time Clock (RTC)
      3. 4.2.3  RESET, Interrupts, and JTAG
      4. 4.2.4  Inter-Integrated Circuit (I2C)
      5. 4.2.5  Inter-IC Sound (I2S)
      6. 4.2.6  Serial Peripheral Interface (SPI)
      7. 4.2.7  Universal Asynchronous Receiver/Transmitter (UART)
      8. 4.2.8  Universal Serial Bus (USB) 2.0
      9. 4.2.9  LCD Bridge
      10. 4.2.10 Secure Digital (SD)
        1. 4.2.10.1 SD1 Signal Descriptions
        2. 4.2.10.2 SD0 Signal Descriptions
      11. 4.2.11 Successive Approximation (SAR) Analog-to-Digital Converter (ADC)
      12. 4.2.12 General-Purpose Input/Output (GPIO)
      13. 4.2.13 Regulators and Power Management
      14. 4.2.14 Reserved and No Connects
      15. 4.2.15 Supply Voltage
      16. 4.2.16 Ground
    3. 4.3 Pin Multiplexing
      1. 4.3.1 LCD Controller, SPI, UART, I2S2, I2S3, and GP[31:27, 20:12] Pin Multiplexing [EBSR.PPMODE Bits] — C5535 Only
      2. 4.3.2 SD1, I2S1, and GP[11:6] Pin Multiplexing [EBSR.SP1MODE Bits]
      3. 4.3.3 SD0, I2S0, and GP[5:0] Pin Multiplexing [EBSR.SP0MODE Bits]
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Electrical Characteristics
    4. 5.4 Handling Ratings
    5. 5.5 Thermal Characteristics
    6. 5.6 Power-On Hours
    7. 5.7 Timing and Switching Characteristics
      1. 5.7.1  Parameter Information
        1. 5.7.1.1 1.8-V, 2.5-V, 2.75-V, and 3.3-V Signal Transition Levels
        2. 5.7.1.2 3.3-V Signal Transition Rates
        3. 5.7.1.3 Timing Parameters and Board Routing Analysis
      2. 5.7.2  Power Supplies
        1. 5.7.2.1 Power Considerations for C5535 and C5534
          1. 5.7.2.1.1 LDO Configuration
            1. 5.7.2.1.1.1 LDO Inputs
            2. 5.7.2.1.1.2 LDO Outputs
            3. 5.7.2.1.1.3 LDO Control
        2. 5.7.2.2 Power Considerations for C5533
          1. 5.7.2.2.1 LDO Configuration
            1. 5.7.2.2.1.1 LDO Inputs
            2. 5.7.2.2.1.2 LDO Outputs
            3. 5.7.2.2.1.3 LDO Control
        3. 5.7.2.3 Power Considerations for C5532
          1. 5.7.2.3.1 LDO Configuration
          2. 5.7.2.3.2 LDO Inputs
          3. 5.7.2.3.3 LDO Outputs
        4. 5.7.2.4 Power-Supply Sequencing
        5. 5.7.2.5 Digital I/O Behavior When Core Power (CVDD) is Down
        6. 5.7.2.6 Power-Supply Design Considerations
        7. 5.7.2.7 Power-Supply Decoupling
        8. 5.7.2.8 LDO Input Decoupling
        9. 5.7.2.9 LDO Output Decoupling
      3. 5.7.3  Reset
        1. 5.7.3.1 Power-On Reset (POR) Circuits
          1. 5.7.3.1.1 RTC Power-On Reset (POR)
          2. 5.7.3.1.2 Main Power-On Reset (POR)
          3. 5.7.3.1.3 Reset Pin (RESET)
        2. 5.7.3.2 Pin Behavior at Reset
        3. 5.7.3.3 Reset Electrical Data and Timing
        4. 5.7.3.4 Configurations at Reset
          1. 5.7.3.4.1 Device and Peripheral Configurations at Device Reset
        5. 5.7.3.5 Configurations After Reset
          1. 5.7.3.5.1 External Bus Selection Register (EBSR)
          2. 5.7.3.5.2 LDO Control Register [7004h]
          3. 5.7.3.5.3 USB System Control Registers (USBSCR) [1C32h]
          4. 5.7.3.5.4 Peripheral Clock Gating Control Registers (PCGCR1 and PCGCR2) [1C02h and 1C03h]
          5. 5.7.3.5.5 Pullup and Pulldown Inhibit Registers (PDINHIBR1, 2, and 3) [1C17h, 1C18h, and 1C19h]
          6. 5.7.3.5.6 Output Slew Rate Control Register (OSRCR) [1C16h]
      4. 5.7.4  Clock Specifications
        1. 5.7.4.1 Recommended Clock and Control Signal Transition Behavior
        2. 5.7.4.2 Clock Considerations
          1. 5.7.4.2.1 Clock Configurations After Device Reset
            1. 5.7.4.2.1.1 Device Clock Frequency
            2. 5.7.4.2.1.2 Peripheral Clock State
            3. 5.7.4.2.1.3 USB Oscillator Control
        3. 5.7.4.3 PLLs
          1. 5.7.4.3.1 PLL Device-Specific Information
          2. 5.7.4.3.2 Clock PLL Considerations With External Clock Sources
          3. 5.7.4.3.3 External Clock Input From RTC_XI, CLKIN, and USB_MXI Pins
            1. 5.7.4.3.3.1 Real-Time Clock (RTC) On-Chip Oscillator With External Crystal
            2. 5.7.4.3.3.2 CLKIN Pin With LVCMOS-Compatible Clock Input (Optional)
            3. 5.7.4.3.3.3 USB On-Chip Oscillator With External Crystal (Optional)
        4. 5.7.4.4 Input and Output Clocks Electrical Data and Timing
        5. 5.7.4.5 Wake-up Events, Interrupts, and XF
          1. 5.7.4.5.1 Interrupts Electrical Data and Timing
          2. 5.7.4.5.2 Wake Up From IDLE Electrical Data and Timing
          3. 5.7.4.5.3 XF Electrical Data and Timing
      5. 5.7.5  Direct Memory Access (DMA) Controller
        1. 5.7.5.1 DMA Channel Synchronization Events
      6. 5.7.6  General-Purpose Input/Output
        1. 5.7.6.1 GPIO Peripheral Input/Output Electrical Data and Timing
        2. 5.7.6.2 GPIO Peripheral Input Latency Electrical Data and Timing
      7. 5.7.7  General-Purpose Timers
      8. 5.7.8  Inter-Integrated Circuit (I2C)
        1. 5.7.8.1 I2C Electrical Data and Timing
      9. 5.7.9  Inter-IC Sound (I2S)
        1. 5.7.9.1 I2S Electrical Data and Timing
      10. 5.7.10 Liquid Crystal Display Controller (LCDC) — C5535 Only
        1. 5.7.10.1 LCDC Electrical Data and Timing
      11. 5.7.11 Real-Time Clock (RTC)
        1. 5.7.11.1 RTC-Only Mode
      12. 5.7.12 SAR ADC (10-Bit) — C5535 Only
        1. 5.7.12.1 SAR ADC Electrical Data and Timing
      13. 5.7.13 Secure Digital (SD)
        1. 5.7.13.1 SD Electrical Data and Timing
      14. 5.7.14 Serial Port Interface (SPI)
        1. 5.7.14.1 SPI Electrical Data and Timing
      15. 5.7.15 Universal Asynchronous Receiver/Transmitter (UART)
        1. 5.7.15.1 UART Electrical Data and Timing [Receive and Transmit]
      16. 5.7.16 Universal Serial Bus (USB) 2.0 Controller — Does Not Apply to C5532
        1. 5.7.16.1 USB 2.0 Electrical Data and Timing
      17. 5.7.17 Emulation and Debug
        1. 5.7.17.1 Debugging Considerations
          1. 5.7.17.1.1 Pullup and Pulldown Resistors
          2. 5.7.17.1.2 Bus Holders
          3. 5.7.17.1.3 CLKOUT Pin
      18. 5.7.18 IEEE 1149.1 JTAG
        1. 5.7.18.1 JTAG Test_port Electrical Data and Timing
  6. 6Detailed Description
    1. 6.1 CPU
    2. 6.2 Memory
      1. 6.2.1 Internal Memory
        1. 6.2.1.1 On-Chip Dual-Access RAM (DARAM)
        2. 6.2.1.2 On-Chip Read-Only Memory (ROM)
        3. 6.2.1.3 On-Chip Single-Access RAM (SARAM)
          1. 6.2.1.3.1 SARAM for C5535
          2. 6.2.1.3.2 SARAM for C5534
          3. 6.2.1.3.3 SARAM for C5533
        4. 6.2.1.4 I/O Memory
      2. 6.2.2 Memory Map
      3. 6.2.3 Register Map
        1. 6.2.3.1  General-Purpose Input/Output Peripheral Register Descriptions
        2. 6.2.3.2  I2C Peripheral Register Descriptions
        3. 6.2.3.3  I2S Peripheral Register Descriptions
        4. 6.2.3.4  LCDC Peripheral Register Descriptions
        5. 6.2.3.5  RTC Peripheral Register Descriptions
        6. 6.2.3.6  SAR ADC Peripheral Register Descriptions
        7. 6.2.3.7  SD Peripheral Register Descriptions
        8. 6.2.3.8  SPI Peripheral Register Descriptions
        9. 6.2.3.9  System Registers
        10. 6.2.3.10 Timers Peripheral Register Descriptions
        11. 6.2.3.11 UART Peripheral Register Descriptions
        12. 6.2.3.12 USB2.0 Peripheral Register Descriptions
    3. 6.3 Identification
      1. 6.3.1 JTAG Identification
    4. 6.4 Boot Modes
      1. 6.4.1 Invocation Sequence
      2. 6.4.2 Boot Configuration
      3. 6.4.3 DSP Resources Used By the Bootloader
  7. 7Device and Documentation Support
    1. 7.1 Device Support
      1. 7.1.1 Development Support
      2. 7.1.2 Device Nomenclature
    2. 7.2 Documentation Support
      1. 7.2.1 Related Documentation
    3. 7.3 Related Links
    4. 7.4 社区资源
    5. 7.5 商标
    6. 7.6 静电放电警告
    7. 7.7 Glossary
  8. 8Mechanical Packaging and Orderable Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • ZAY|144
散热焊盘机械数据 (封装 | 引脚)
订购信息

2 修订历史记录

Changes from B Revision (February, 2012) to C Revision

  • Added power-on information for USB_VBUS, USB_VDDA3P3, USB_VDDA1P3, and USB_VDD1P3 (LitBug SDOCM00101620)Go
  • Changed description for RSV6 to tie directly to Vss (LitBug SDOCM00101619)Go
  • Changed values for ESD Stress Voltage. HBM changed to > 1000 VGo
  • Added note that CVDDRTC must always be powered by an external power source and cannot be powered by on-chip LDOs (Bugzilla 2151)Go
  • Changed WU_DOUT reset value to 1 (LitBug SDOCM00096670)Go
  • Added steps to Power-Supply Sequencing when USB subsystem is used (LitBug SDOCM00101620)Go
  • Deleted unsupported EMIF pins (LitBug SDOCM00095615)Go
  • Changed PLLOUT minimum to 60, maximum to 120 (LitBug SDOCM00097379)Go
  • Changed SYSCLK maximum to 50 (Bugzilla 2145)Go
  • Changed PLL_LOCKTIME to 4 ms maximum from 4 ms minimum (LitBug SDOCM00097381)Go
  • Changed minimum value for timing requirement for Wake-Up From IDLE (LitBug SDOCM00096476)Go
  • Changed description of switching characteristic parameter for Wake-Up From IDLE (LitBug SDOCM00096480)Go
  • Changed timing diagram for Wake-Up From IDLE (LitBug SDOCM00096480)Go
  • Added hardware requirement for RTC-Only Mode to verify the USB oscillator is disabled (LitBug SDOCM00097368)Go
  • Changed addresses for SD0 and SD1 in Peripheral I/O-Space Control Registers (LitBug SDOCM00101622)Go
  • Added step to copy boot image sections to system memory (TIS Doc Feedback ID 5979)Go
  • Changed Bootloader Software Architecture (TIS Doc Feedback ID 5979)Go
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