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Table 5-23 McBSP Switching Characteristics⁽¹⁾⁽²⁾

NO.	PARAMETER			MIN	MAX	UNIT
1	t_{d(CKSH-CKRXH)}	Delay time, CLKS high to CLKR/X high for internal CLKR/X generated from CLKS input.		1	14.5	ns
2	t_c(CKRX)	Cycle time, CLKR/X	CLKR/X int	2P or 20⁽³⁾⁽⁴⁾		ns
3	t_w(CKRX)	Pulse duration, CLKR/X high or CLKR/X low	CLKR/X int	C – 2⁽⁵⁾	C + 2⁽⁵⁾	ns
4	t_d(CKRH-FRV)	Delay time, CLKR high to internal FSR valid	CLKR int	–4	5.5	ns
4	t_d(CKRH-FRV)	Delay time, CLKR high to internal FSR valid	CLKR int	1	14.5	ns
9	t_d(CKXH-FXV)	Delay time, CLKX high to internal FSX valid	CLKX int	–4	5.5	ns
9	t_d(CKXH-FXV)	Delay time, CLKX high to internal FSX valid	CLKX ext	1	14.5	ns
12	t_{dis(CKXH-DXHZ)}	Disable time, DX Hi-Z following last data bit from CLKX high	CLKX int	–4	7.5	ns
12	t_{dis(CKXH-DXHZ)}		CLKX ext	1	14.5	ns
13	t_d(CKXH-DXV)	Delay time, CLKX high to DX valid	CLKX int	–4 + D1⁽⁶⁾	5.5 + D2⁽⁶⁾	ns
13	t_d(CKXH-DXV)	Delay time, CLKX high to DX valid	CLKX ext	1 + D1⁽⁶⁾	14.5 + D2⁽⁶⁾	ns
14	t_d(FXH-DXV)	Delay time, FSX high to DX valid applies ONLY when in data delay 0 (XDATDLY = 00b) mode	FSX int	–4 + D1⁽⁷⁾	5 + D2⁽⁷⁾	ns
14	t_d(FXH-DXV)		FSX ext	–2 + D1⁽⁷⁾	14.5 + D2⁽⁷⁾	ns

(1) CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.

(2) Minimum delay times also represent minimum output hold times.

(3) P = SYSCLK7 period in ns. For example, when the SYSCLK7 clock domain is running at 166 MHz, use 6 ns.

(4) Use whichever value is greater.

(5) C = H or L
S = sample rate generator input clock = P if CLKSM = 1 (P = SYSCLK7 period)
S = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
If CLKGDV is even:
(1) H = CLKX high pulse width = (CLKGDV/2 + 1) * S
(2) L = CLKX low pulse width = (CLKGDV/2) * S
If CLKGDV is odd:
(1) H = (CLKGDV + 1)/2 * S
(2) L = (CLKGDV + 1)/2 * S
CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit.

(6) Extra delay from CLKX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
if DXENA = 0, then D1 = D2 = 0
if DXENA = 1, then D1 = 4P, D2 = 8P

(7) Extra delay from FSX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
if DXENA = 0, then D1 = D2 = 0
if DXENA = 1, then D1 = 4P, D2 = 8P

TMS320C6652 TMS320C6654 McBSP_timing.gif

Figure 5-25 McBSP Timing

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Table 5-23 McBSP Switching Characteristics⁽¹⁾⁽²⁾

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Table 5-23 McBSP Switching Characteristics(1)(2)

Table 5-23 McBSP Switching Characteristics⁽¹⁾⁽²⁾