ZHCSDR5B March   2012  – April 2015 TMS320C6654

PRODUCTION DATA.  

  1. 1 C6654 特性和描述
    1. 1.1 特性
    2. 1.2 KeyStone 架构
    3. 1.3 器件描述
    4. 1.4 功能方框图
  2. 2 修订历史记录
  3. 3 Device Overview
    1. 3.1 Device Characteristics
    2. 3.2 DSP Core Description
    3. 3.3 Memory Map Summary
    4. 3.4 Boot Sequence
    5. 3.5 Boot Modes Supported and PLL Settings
      1. 3.5.1 Boot Device Field
      2. 3.5.2 Device Configuration Field
        1. 3.5.2.1 EMIF16 / UART / No Boot Device Configuration
          1. 3.5.2.1.1 No Boot Mode
          2. 3.5.2.1.2 UART Boot Mode
          3. 3.5.2.1.3 EMIF16 Boot Mode
        2. 3.5.2.2 Ethernet (SGMII) Boot Device Configuration
        3. 3.5.2.3 NAND Boot Device Configuration
        4. 3.5.2.4 PCI Boot Device Configuration
        5. 3.5.2.5 I2C Boot Device Configuration
          1. 3.5.2.5.1 I2C Master Mode
          2. 3.5.2.5.2 I2C Passive Mode
        6. 3.5.2.6 SPI Boot Device Configuration
      3. 3.5.3 Boot Parameter Table
        1. 3.5.3.1 Sleep / XIP Mode Parameter Table
        2. 3.5.3.2 SRIO Mode Boot Parameter Table
        3. 3.5.3.3 Ethernet Mode Boot Parameter Table
        4. 3.5.3.4 NAND Mode Boot Parameter Table
        5. 3.5.3.5 PCIE Mode Boot Parameter Table
        6. 3.5.3.6 I2C Mode Boot Parameter Table
        7. 3.5.3.7 SPI Mode Boot Parameter Table
        8. 3.5.3.8 Hyperlink Mode Boot Parameter Table
        9. 3.5.3.9 UART Mode Boot Parameter Table
    6. 3.6 PLL Boot Configuration Settings
    7. 3.7 Second-Level Bootloaders
    8. 3.8 Terminals
      1. 3.8.1 Package Terminals
      2. 3.8.2 Pin Map
    9. 3.9 Terminal Functions
  4. 4 Device Configuration
    1. 4.1 Device Configuration at Device Reset
    2. 4.2 Peripheral Selection After Device Reset
    3. 4.3 Device State Control Registers
      1. 4.3.1  Device Status Register
      2. 4.3.2  Device Configuration Register
      3. 4.3.3  JTAG ID (JTAGID) Register Description
      4. 4.3.4  Kicker Mechanism (KICK0 and KICK1) Register
      5. 4.3.5  LRESETNMI PIN Status (LRSTNMIPINSTAT) Register
      6. 4.3.6  LRESETNMI PIN Status Clear (LRSTNMIPINSTAT_CLR) Register
      7. 4.3.7  Reset Status (RESET_STAT) Register
      8. 4.3.8  Reset Status Clear (RESET_STAT_CLR) Register
      9. 4.3.9  Boot Complete (BOOTCOMPLETE) Register
      10. 4.3.10 Power State Control (PWRSTATECTL) Register
      11. 4.3.11 NMI Event Generation to CorePac (NMIGRx) Register
      12. 4.3.12 IPC Generation (IPCGRx) Registers
      13. 4.3.13 IPC Acknowledgement (IPCARx) Registers
      14. 4.3.14 IPC Generation Host (IPCGRH) Register
      15. 4.3.15 IPC Acknowledgement Host (IPCARH) Register
      16. 4.3.16 Timer Input Selection Register (TINPSEL)
      17. 4.3.17 Timer Output Selection Register (TOUTPSEL)
      18. 4.3.18 Reset Mux (RSTMUXx) Register
      19. 4.3.19 Device Speed (DEVSPEED) Register
      20. 4.3.20 Pin Control 0 (PIN_CONTROL_0) Register
      21. 4.3.21 Pin Control 1 (PIN_CONTROL_1) Register
      22. 4.3.22 uPP Clock Source (UPP_CLOCK) Register
    4. 4.4 Pullup/Pulldown Resistors
  5. 5 System Interconnect
    1. 5.1 Internal Buses and Switch Fabrics
    2. 5.2 Switch Fabric Connections Matrix
    3. 5.3 TeraNet Switch Fabric Connections
    4. 5.4 Bus Priorities
      1. 5.4.1 Packet DMA Priority Allocation (PKTDMA_PRI_ALLOC) Register
      2. 5.4.2 EMAC / uPP Priority Allocation (EMAC_UPP_PRI_ALLOC) Register
  6. 6 C66x CorePac
    1. 6.1 Memory Architecture
      1. 6.1.1 L1P Memory
      2. 6.1.2 L1D Memory
      3. 6.1.3 L2 Memory
      4. 6.1.4 MSM Controller
      5. 6.1.5 L3 Memory
    2. 6.2 Memory Protection
    3. 6.3 Bandwidth Management
    4. 6.4 Power-Down Control
    5. 6.5 C66x CorePac Revision
    6. 6.6 C66x CorePac Register Descriptions
  7. 7 Device Operating Conditions
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Recommended Operating Conditions
    3. 7.3 Electrical Characteristics
    4. 7.4 Power Supply to Peripheral I/O Mapping
  8. 8 Peripheral Information and Electrical Specifications
    1. 8.1  Recommended Clock and Control Signal Transition Behavior
    2. 8.2  Power Supplies
      1. 8.2.1 Power-Supply Sequencing
        1. 8.2.1.1 Core-Before-IO Power Sequencing
        2. 8.2.1.2 IO-Before-Core Power Sequencing
        3. 8.2.1.3 Prolonged Resets
        4. 8.2.1.4 Clocking During Power Sequencing
      2. 8.2.2 Power-Down Sequence
      3. 8.2.3 Power Supply Decoupling and Bulk Capacitors
      4. 8.2.4 SmartReflex
    3. 8.3  Power Sleep Controller (PSC)
      1. 8.3.1 Power Domains
      2. 8.3.2 Clock Domains
      3. 8.3.3 PSC Register Memory Map
    4. 8.4  Reset Controller
      1. 8.4.1 Power-on Reset
      2. 8.4.2 Hard Reset
      3. 8.4.3 Soft Reset
      4. 8.4.4 Local Reset
      5. 8.4.5 Reset Priority
      6. 8.4.6 Reset Controller Register
      7. 8.4.7 Reset Electrical Data / Timing
    5. 8.5  Main PLL and PLL Controller
      1. 8.5.1 Main PLL Controller Device-Specific Information
        1. 8.5.1.1 Internal Clocks and Maximum Operating Frequencies
        2. 8.5.1.2 Main PLL Controller Operating Modes
        3. 8.5.1.3 Main PLL Stabilization, Lock, and Reset Times
      2. 8.5.2 PLL Controller Memory Map
        1. 8.5.2.1 PLL Secondary Control Register (SECCTL)
        2. 8.5.2.2 PLL Controller Divider Register (PLLDIV2, PLLDIV5, PLLDIV8)
        3. 8.5.2.3 PLL Controller Clock Align Control Register (ALNCTL)
        4. 8.5.2.4 PLLDIV Divider Ratio Change Status Register (DCHANGE)
        5. 8.5.2.5 SYSCLK Status Register (SYSTAT)
        6. 8.5.2.6 Reset Type Status Register (RSTYPE)
        7. 8.5.2.7 Reset Control Register (RSTCTRL)
        8. 8.5.2.8 Reset Configuration Register (RSTCFG)
        9. 8.5.2.9 Reset Isolation Register (RSISO)
      3. 8.5.3 Main PLL Control Register
      4. 8.5.4 Main PLL and PLL Controller Initialization Sequence
      5. 8.5.5 Main PLL Controller/PCIe Clock Input Electrical Data/Timing
    6. 8.6  DDR3 PLL
      1. 8.6.1 DDR3 PLL Control Register
      2. 8.6.2 DDR3 PLL Device-Specific Information
      3. 8.6.3 DDR3 PLL Initialization Sequence
      4. 8.6.4 DDR3 PLL Input Clock Electrical Data/Timing
    7. 8.7  Enhanced Direct Memory Access (EDMA3) Controller
      1. 8.7.1 EDMA3 Device-Specific Information
      2. 8.7.2 EDMA3 Channel Controller Configuration
      3. 8.7.3 EDMA3 Transfer Controller Configuration
      4. 8.7.4 EDMA3 Channel Synchronization Events
    8. 8.8  Interrupts
      1. 8.8.1 Interrupt Sources and Interrupt Controller
      2. 8.8.2 CIC Registers
        1. 8.8.2.1 CIC0 Register Map
        2. 8.8.2.2 CIC1 Register Map
      3. 8.8.3 Inter-Processor Register Map
      4. 8.8.4 NMI and LRESET
      5. 8.8.5 External Interrupts Electrical Data/Timing
    9. 8.9  Memory Protection Unit (MPU)
      1. 8.9.1 MPU Registers
        1. 8.9.1.1 MPU Register Map
        2. 8.9.1.2 Device-Specific MPU Registers
          1. 8.9.1.2.1 Configuration Register (CONFIG)
      2. 8.9.2 MPU Programmable Range Registers
        1. 8.9.2.1 Programmable Range n Start Address Register (PROGn_MPSAR)
        2. 8.9.2.2 Programmable Range n End Address Register (PROGn_MPEAR)
        3. 8.9.2.3 Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPA)
        4. 8.9.2.4 MPU Registers Reset Values
    10. 8.10 DDR3 Memory Controller
      1. 8.10.1 DDR3 Memory Controller Device-Specific Information
      2. 8.10.2 DDR3 Memory Controller Electrical Data/Timing
    11. 8.11 I2C Peripheral
      1. 8.11.1 I2C Device-Specific Information
      2. 8.11.2 I2C Peripheral Register Description(s)
      3. 8.11.3 I2C Electrical Data/Timing
        1. 8.11.3.1 Inter-Integrated Circuits (I2C) Timing
    12. 8.12 SPI Peripheral
      1. 8.12.1 SPI Electrical Data/Timing
        1. 8.12.1.1 SPI Timing
    13. 8.13 UART Peripheral
    14. 8.14 PCIe Peripheral
    15. 8.15 EMIF16 Peripheral
      1. 8.15.1 EMIF16 Electrical Data/Timing
    16. 8.16 Ethernet Media Access Controller (EMAC)
      1. 8.16.1 EMAC Device-Specific Information
      2. 8.16.2 EMAC Peripheral Register Description(s)
      3. 8.16.3 EMAC Electrical Data/Timing (SGMII)
    17. 8.17 Management Data Input/Output (MDIO)
      1. 8.17.1 MDIO Peripheral Registers
      2. 8.17.2 MDIO Timing
    18. 8.18 Timers
      1. 8.18.1 Timers Device-Specific Information
      2. 8.18.2 Timers Electrical Data/Timing
    19. 8.19 General-Purpose Input/Output (GPIO)
      1. 8.19.1 GPIO Device-Specific Information
      2. 8.19.2 GPIO Electrical Data/Timing
    20. 8.20 Semaphore2
    21. 8.21 Multichannel Buffered Serial Port (McBSP)
      1. 8.21.1 McBSP Peripheral Register
      2. 8.21.2 McBSP Electrical Data/Timing
        1. 8.21.2.1 McBSP Timing
    22. 8.22 Universal Parallel Port (uPP)
      1. 8.22.1 uPP Register Descriptions
    23. 8.23 Emulation Features and Capability
      1. 8.23.1 Advanced Event Triggering (AET)
      2. 8.23.2 Trace
        1. 8.23.2.1 Trace Electrical Data/Timing
      3. 8.23.3 IEEE 1149.1 JTAG
        1. 8.23.3.1 IEEE 1149.1 JTAG Compatibility Statement
        2. 8.23.3.2 JTAG Electrical Data/Timing
  9. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
      2. 9.1.2 Device and Development-Support Tool Nomenclature
    2. 9.2 Documentation Support
      1. 9.2.1 Related Links
      2. 9.2.2 社区资源
    3. 9.3 商标
    4. 9.4 静电放电警告
    5. 9.5 Glossary
  10. 10Mechanical Data
    1. 10.1 Thermal Data
    2. 10.2 Packaging Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • CZH|625
散热焊盘机械数据 (封装 | 引脚)
订购信息

9 Device and Documentation Support

9.1 Device Support

9.1.1 Development Support

In case the customer would like to develop their own features and software on the C6654 device, TI offers an extensive line of development tools for the TMS320C6000™ DSP platform, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. The tool's support documentation is electronically available within the Code Composer Studio™ Integrated Development Environment (IDE).

The following products support development of C6000™ DSP-based applications:

  • Software Development Tools:
    • Code Composer Studio™ Integrated Development Environment (IDE), including Editor C/C++/Assembly Code Generation, and Debug plus additional development tools.
    • Scalable, Real-Time Foundation Software (DSP/BIOS™), which provides the basic run-time target software needed to support any DSP application.
  • Hardware Development Tools:
    • Extended Development System (XDS™) Emulator (supports C6000™ DSP multiprocessor system debug)
    • EVM (Evaluation Module)

9.1.2 Device and Development-Support Tool Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all DSP devices and support tools. Each DSP commercial family member has one of three prefixes: TMX, TMP, or TMS (e.g., TMX320CMH). Texas Instruments recommends two of three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS).

Device development evolutionary flow:

  • TMX: Experimental device that is not necessarily representative of the final device's electrical specifications
  • TMP: Final silicon die that conforms to the device's electrical specifications but has not completed quality and reliability verification
  • TMS: Fully qualified production device

Support tool development evolutionary flow:

  • TMDX: Development-support product that has not yet completed Texas Instruments internal qualification testing.
  • TMDS: Fully qualified development-support product

TMX and TMP devices and TMDX development-support tools are shipped with the following disclaimer:

  • "Developmental product is intended for internal evaluation purposes."

TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI's standard warranty applies.

Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used.

TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, CZH), the temperature range (for example, blank is the default case temperature range), and the device speed range, in Megahertz (for example, blank is 1000 MHz [1 GHz]).

For device part numbers and further ordering information for C6654 in the CZH or GZH package type, see the TI website www.ti.com or contact your TI sales representative.

Figure 9-1 provides a legend for reading the complete device name for any C66x KeyStone device.

TMS320C6654 Device_Nomenclature_6654.gifFigure 9-1 C66x DSP Device Nomenclature (including the C6654)

9.2 Documentation Support

These documents describe the C6654 Fixed and Floating-Point Digital Signal Processor. Copies of these documents are available on the Internet at www.ti.com.

64-bit Timer (Timer 64) for KeyStone Devices User's Guide SPRUGV5
Bootloader for the C66x DSP User's Guide SPRUGY5
C66x CorePac User's Guide SPRUGW0
C66x CPU and Instruction Set Reference Guide SPRUGH7
C66x DSP Cache User's Guide SPRUGY8
DDR3 Design Guide for KeyStone Devices SPRABI1
DDR3 Memory Controller for KeyStone Devices User's Guide SPRUGV8
DSP Power Consumption Summary for KeyStone Devices SPRABL4
Debug and Trace for KeyStone I Devices User's Guide SPRUGZ2
Emulation and Trace Headers Technical Reference SPRU655
Enhanced Direct Memory Access 3 (EDMA3) for KeyStone Devices User's Guide SPRUGS5
External Memory Interface (EMIF16) for KeyStone Devices User's Guide SPRUGZ3
General Purpose Input/Output (GPIO) for KeyStone Devices User's Guide SPRUGV1
Gigabit Ethernet (GbE) Subsystem for KeyStone Devices User's Guide SPRUGV9
Hardware Design Guide for KeyStone Devices SPRABI2
Inter Integrated Circuit (I2C) for KeyStone Devices User's Guide SPRUGV3
Chip Interrupt Controller (CIC) for KeyStone Devices User's Guide SPRUGW4
Memory Protection Unit (MPU) for KeyStone Devices User's Guide SPRUGW5
Multichannel Buffered Serial Port (McBSP) for KeyStone Devices User's Guide
Multicore Navigator for KeyStone Devices User's Guide SPRUGR9
Multicore Shared Memory Controller (MSMC) for KeyStone Devices User's Guide SPRUGW7
Peripheral Component Interconnect Express (PCIe) for KeyStone Devices User's Guide SPRUGS6
Phase Locked Loop (PLL) for KeyStone Devices User's Guide SPRUGV2
Power Sleep Controller (PSC) for KeyStone Devices User's Guide SPRUGV4
Semaphore2 Hardware Module for KeyStone Devices User's Guide SPRUGS3
Serial Peripheral Interface (SPI) for KeyStone Devices User's Guide SPRUGP2
Universal Asynchronous Receiver/Transmitter (UART) for KeyStone Devices User's Guide SPRUGP1
Universal Parallel Port (uPP) for KeyStone Devices User's Guide
Using Advanced Event Triggering to Debug Real-Time Problems in High Speed Embedded Microprocessor Systems SPRA387
Using Advanced Event Triggering to Find and Fix Intermittent Real-Time Bugs SPRA753
Using IBIS Models for Timing Analysis SPRA839

9.2.1 Related Links

The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy.

Table 9-1 Related Links

PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY
TMS320C6654 Click here Click here Click here Click here Click here

9.2.2 社区资源

下列链接提供到 TI 社区资源的连接。 链接的内容由各个分销商“按照原样”提供。 这些内容并不构成 TI 技术规范和标准且不一定反映 TI 的观点；请见 TI 的使用条款。

    TI E2E™ 在线社区 TI 工程师对工程师 (E2E) 社区。 此社区的创建目的是为了促进工程师之间协作。 在 e2e.ti.com 中，您可以咨询问题、共享知识、探索思路，在同领域工程师的帮助下解决问题。
    米6体育平台手机版_好二三四 (TI) 嵌入式处理器维基网站 米6体育平台手机版_好二三四 (TI) 嵌入式处理器维基网站。 此网站的建立是为了帮助开发人员从米6体育平台手机版_好二三四 (TI) 的嵌入式处理器入门并且也为了促进与这些器件相关的硬件和软件的总体知识的创新和增长。

9.3 商标

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

9.4 静电放电警告

esds-image

ESD 可能会损坏该集成电路。米6体育平台手机版_好二三四 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可能会导致器件与其发布的规格不相符。

9.5 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.
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