SPRS814D March 2012 – October 2019 TMS320C6655 , TMS320C6657
PRODUCTION DATA.
请参考 PDF 数据表获取器件具体的封装图。
The EDMA3 supports up to 64 DMA channels for EDMA3_CC that can be used to service system peripherals and to move data between system memories. DMA channels can be triggered by synchronization events generated by system peripherals. Table 6-25 lists the source of the synchronization event associated with each of the EDMA3_CC DMA channels. On the C665x, the association of each synchronization event and DMA channel is fixed and cannot be reprogrammed.
For more detailed information on the EDMA3 module and how EDMA3 events are enabled, captured, processed, prioritized, linked, chained, and cleared, and so forth, see the Enhanced Direct Memory Access 3 (EDMA3) for KeyStone Devices User's Guide.
EVENT NUMBER | EVENT | EVENT DESCRIPTION |
---|---|---|
0 | TCP3D_AREVT0 | TCP3D_A receive event0 |
1 | TCP3D_AREVT1 | TCP3D_A receive event1 |
2 | TINT2L | Timer2 interrupt low |
3 | TINT2H | Timer2 interrupt high |
4 | URXEVT | UART0 receive event |
5 | UTXEVT | UART0 transmit event |
6 | GPINT0 | GPIO interrupt |
7 | GPINT1 | GPIO interrupt |
8 | GPINT2 | GPIO Interrupt |
9 | GPINT3 | GPIO interrupt |
10 | VCPAREVT | VCP2_A receive event |
11 | VCPAXEVT | VCP2_A transmit event |
12 | VCPBREVT | VCP2_B receive event |
13 | VCPBXEVT | VCP2_B transmit event |
14 | URXEVT_B | UART1 receive event |
15 | UTXEVT_B | UART1 transmit event |
16 | SPIINT0 | SPI interrupt |
17 | SPIINT1 | SPI interrupt |
18 | SEMINT0 | Semaphore interrupt |
19 | SEMINT1 | Semaphore interrupt |
20 | SEMINT2 | Semaphore interrupt |
21 | SEMINT3 | Semaphore interrupt |
22 | TINT4L | Timer4 interrupt low |
23 | TINT4H | Timer4 interrupt high |
24 | TINT5L | Timer5 interrupt low |
25 | TINT5H | Timer5 interrupt high |
26 | TINT6L | Timer6 interrupt low |
27 | TINT6H | Timer6 interrupt high |
28 | TINT7L | Timer7 interrupt low |
29 | TINT7H | Timer7 interrupt high |
30 | SPIXEVT | SPI transmit event |
31 | SPIREVT | SPI receive event |
32 | I2CREVET | I2C receive event |
33 | I2CXEVT | I2C transmit event |
34 | TINT3L | Timer3 interrupt low |
35 | TINT3H | Timer3 interrupt high |
36 | MCBSP0_REVT | McBSP_0 receive event |
37 | MCBSP0_XEVT | McBSP_0 transmit event |
38 | MCBSP1_REVT | McBSP_1 receive event |
39 | MCBSP1_XEVT | McBSP_1 transmit event |
40 | TETBHFULLINT | TETB half full interrupt |
41 | TETBHFULLINT0 | TETB half full interrupt |
42 | TETBHFULLINT1 | TETB half full interrupt |
43 | CIC1_OUT0 | Interrupt Controller output |
44 | CIC1_OUT1 | Interrupt Controller output |
45 | CIC1_OUT2 | Interrupt Controller output |
46 | CIC1_OUT3 | Interrupt Controller output |
47 | CIC1_OUT4 | Interrupt Controller output |
48 | CIC1_OUT5 | Interrupt Controller output |
49 | CIC1_OUT6 | Interrupt Controller output |
50 | CIC1_OUT7 | Interrupt Controller output |
51 | CIC1_OUT8 | Interrupt Controller output |
52 | CIC1_OUT9 | Interrupt Controller output |
53 | CIC1_OUT10 | Interrupt Controller output |
54 | CIC1_OUT11 | Interrupt Controller output |
55 | CIC1_OUT12 | Interrupt Controller output |
56 | CIC1_OUT13 | Interrupt Controller output |
57 | CIC1_OUT14 | Interrupt Controller output |
58 | CIC1_OUT15 | Interrupt Controller output |
59 | CIC1_OUT16 | Interrupt Controller output |
60 | CIC1_OUT17 | Interrupt Controller output |
61 | TETBFULLINT | TETB full interrupt |
62 | TETBFULLINT0 | TETB full interrupt |
63 | TETBFULLINT1 | TETB full interrupt |