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SPRS814D March 2012 – October 2019 TMS320C6655 , TMS320C6657

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CZH|625
GZH|625

散热焊盘机械数据 (封装 | 引脚)

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5.7.3 Main PLL Stabilization, Lock, and Reset Times

The PLL stabilization time is the amount of time that must be allotted for the internal PLL regulators to become stable after device power up. The PLL should not be operated until this stabilization time has elapsed.

The PLL reset time is the amount of wait time needed when resetting the PLL (writing PLLRST = 1), in order for the PLL to properly reset, before bringing the PLL out of reset (writing PLLRST = 0). For the Main PLL reset time value, see Table 5-5.

The PLL lock time is the amount of time needed from when the PLL is taken out of reset (PLLRST = 1 with PLLEN = 0) to when to when the PLL controller can be switched to PLL mode (PLLEN = 1). The Main PLL lock time is given in Table 5-5.

Table 5-5 Main PLL Stabilization, Lock, and Reset Times

	MIN	MAX	UNIT
PLL stabilization time	100		µs
PLL lock time		500 ×(PLLD⁽¹⁾+1) × C⁽²⁾
PLL reset time	1000		ns

(1) PLLD is the value in PLLD bit fields of MAINPLLCTL0 register

(2) C = SYSCLK1(N|P) cycle time in ns.