Table 6-19 EMIFA Asynchronous Memory Timing Requirements(1)
| NO. |
|
MIN |
NOM |
MAX |
UNIT |
| READS and WRITES |
| E |
tc(CLK) |
Cycle time, EMIFA module clock |
10 |
|
|
ns |
| 2 |
tw(EM_WAIT) |
Pulse duration, EM_WAIT assertion and deassertion |
2E |
|
|
ns |
| READS |
| 12 |
tsu(EMDV-EMOEH) |
Setup time, EMA_D[15:0] valid before EM_OE high |
3 |
|
|
ns |
| 13 |
th(EMOEH-EMDIV) |
Hold time, EMA_D[15:0] valid after EM_OE high |
0 |
|
|
ns |
| 14 |
tsu(EMOEL-EMWAIT) |
Setup time, EM_WAIT asserted before end of Strobe Phase(2) |
4E+3 |
|
|
ns |
| WRITES |
| 28 |
tsu(EMWEL-EMWAIT) |
Setup time, EM_WAIT asserted before end of Strobe Phase(2) |
4E+3 |
|
|
ns |
(1) E = EMA_CLK period or in ns. EMA_CLK is selected either as SYSCLK3 or the PLL output clock divided by 4.5. As an example, when SYSCLK3 is selected and set to 100MHz, E=10ns.
(2) Setup before end of STROBE phase (if no extended wait states are inserted) by which EM_WAIT must be asserted to add extended wait states.
Figure 6-15 and
Figure 6-16 describe EMIF transactions that include extended wait states inserted during the STROBE phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start of where the HOLD phase would begin if there were no extended wait cycles.