6.6 Clock PLLs

The C6745/6747 has one PLL controller that provides clock to different parts of the system. PLL0 provides clocks (though various dividers) to most of the components of the device.

The PLL controller provides the following:

• Glitch-Free Transitions (on changing clock settings)
• Domain Clocks Alignment
• Clock Gating
• PLL power down

The various clock outputs given by the controller are as follows:

• Domain Clocks: SYSCLK [1:n]
• Auxiliary Clock from reference clock source: AUXCLK

Various dividers that can be used are as follows:

• Post-PLL Divider: POSTDIV
• SYSCLK Divider: D1, ¼, Dn

Various other controls supported are as follows:

• PLL Multiplier Control: PLLM
• Software programmable PLL Bypass: PLLEN