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ZHCSGV3G June 2009 – January 2017 TMS320C6748

PRODUCTION DATA.

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)

ZCE|361
ZWT|361

散热焊盘机械数据 (封装 | 引脚)

订购信息

Table 6-114 Switching Characteristics Over Recommended Operating Conditions for Host-Port Interface [1.0V]⁽¹⁾⁽²⁾⁽³⁾

NO.	PARAMETER			1.0V		UNIT
NO.	PARAMETER			MIN	MAX	UNIT
5	t_{d(HSTBL-HRDYV)}	Delay time, HSTROBE low to HRDY valid	For HPI Write, HRDY can go high (not ready) for these HPI Write conditions; otherwise, HRDY stays low (ready): Case 1: Back-to-back HPIA writes (can be either first or second half-word) Case 2: HPIA write following a PREFETCH command (can be either first or second half-word) Case 3: HPID write when FIFO is full or flushing (can be either first or second half-word) Case 4: HPIA write and Write FIFO not empty For HPI Read, HRDY can go high (not ready) for these HPI Read conditions: Case 1: HPID read (with auto-increment) and data not in Read FIFO (can only happen to first half-word of HPID access) Case 2: First half-word access of HPID Read without auto-increment For HPI Read, HRDY stays low (ready) for these HPI Read conditions: Case 1: HPID read with auto-increment and data is already in Read FIFO (applies to either half-word of HPID access) Case 2: HPID read without auto-increment and data is already in Read FIFO (always applies to second half-word of HPID access) Case 3: HPIC or HPIA read (applies to either half-word access)		22	ns
5a	t_{d(HASL-HRDYV)}	Delay time, HAS low to HRDY valid			22	ns
6	t_{en(HSTBL-HDLZ)}	Enable time, HD driven from HSTROBE low		1.5		ns
7	t_d(HRDYL-HDV)	Delay time, HRDY low to HD valid			0	ns
8	t_{oh(HSTBH-HDV)}	Output hold time, HD valid after HSTROBE high		1.5		ns
14	t_{dis(HSTBH-HDHZ)}	Disable time, HD high-impedance from HSTROBE high			22	ns
15	t_d(HSTBL-HDV)	Delay time, HSTROBE low to HD valid	For HPI Read. Applies to conditions where data is already residing in HPID/FIFO: Case 1: HPIC or HPIA read Case 2: First half-word of HPID read with auto-increment and data is already in Read FIFO Case 3: Second half-word of HPID read with or without auto-increment		22	ns
18	t_{d(HSTBH-HRDYV)}	Delay time, HSTROBE high to HRDY valid	For HPI Write, HRDY can go high (not ready) for these HPI Write conditions; otherwise, HRDY stays low (ready): Case 1: HPID write when Write FIFO is full (can happen to either half-word) Case 2: HPIA write (can happen to either half-word) Case 3: HPID write without auto-increment (only happens to second half-word)		22	ns

(1) M=SYSCLK2 period in ns.

(2) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

(3) By design, whenever HCS is driven inactive (high), HPI will drive HRDY active (low).

Figure 6-67 UHPI Read Timing (HAS Not Used, Tied High)

A. For correct operation, strobe the UHPI_HAS signal only once per UHPI_HSTROBE active cycle.

B. UHPI_HSTROBE refers to the following logical operation on UHPI_HCS, UHPI_HDS1, and UHPI_HDS2: [NOT(UHPI_HDS1 XOR UHPI_HDS2)] OR UHPI_HCS.

Figure 6-68 UHPI Read Timing (HAS Used)

Figure 6-69 UHPI Write Timing (HAS Not Used, Tied High)