ZHCSA13P November   2008  – February 2021 TMS320F28020 , TMS320F280200 , TMS320F28021 , TMS320F28022 , TMS320F28023 , TMS320F28023-Q1 , TMS320F28026 , TMS320F28026-Q1 , TMS320F28026F , TMS320F28027 , TMS320F28027-Q1 , TMS320F28027F , TMS320F28027F-Q1

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 功能方框图‎
  5. 5 修订历史记录
  6. 6 Device Comparison
    1. 6.1 Related Products
  7. 7 Terminal Configuration and Functions
    1. 7.1 引脚图
    2. 7.2 信号说明
      1. 7.2.1 信号说明
  8. 8 规格
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD 等级 - 汽车
    3. 8.3  ESD 等级 - 商用
    4. 8.4  建议工作条件
    5. 8.5  功耗摘要
      1. 8.5.1 TMS320F2802x/F280200 在 40MHz SYSCLKOUT 下的电流消耗
      2. 8.5.2 TMS320F2802x 在 50MHz SYSCLKOUT 下的电流消耗
      3. 8.5.3 TMS320F2802x 在 60MHz SYSCLKOUT 下的电流消耗
      4. 8.5.4 Reducing Current Consumption
      5. 8.5.5 流耗图（VREG 启用）
    6. 8.6  电气特性
    7. 8.7  热阻特性
      1. 8.7.1 PT 封装
      2. 8.7.2 DA 封装
    8. 8.8  散热设计注意事项
    9. 8.9  无信号缓冲情况下 MCU 与 JTAG 调试探针的连接
    10. 8.10 参数信息
      1. 8.10.1 时序参数符号
      2. 8.10.2 定时参数的通用注释
    11. 8.11 测试负载电路
    12. 8.12 电源时序
      1. 8.12.1 复位 (XRS) 时序要求
      2. 8.12.2 复位 (XRS) 开关特性
    13. 8.13 时钟规范
      1. 8.13.1 器件时钟表
        1. 8.13.1.1 2802x 时钟表和命名规则（40MHz 器件）
        2. 8.13.1.2 2802x 时钟表和命名规则（50MHz 器件）
        3. 8.13.1.3 2802x时钟表和命名规则（60MHz 器件）
        4. 8.13.1.4 器件计时要求/特性
        5. 8.13.1.5 内部零引脚振荡器 (INTOSC1/INTOSC2) 特性
      2. 8.13.2 时钟要求和特性
        1. 8.13.2.1 XCLKIN 定时要求 - PLL 已启用
        2. 8.13.2.2 XCLKIN 时序要求 - PLL 已禁用
        3. 8.13.2.3 XCLKOUT 开关特性（旁路或启用 PLL）
    14. 8.14 闪存定时
      1. 8.14.1 T 温度材料的闪存/OTP 耐久性
      2. 8.14.2 S 温度材料的闪存/OTP 耐久性
      3. 8.14.3 Q 温度材料的闪存/OTP 耐久性
      4. 8.14.4 60MHz SYSCLKOUT 下的闪存参数
      5. 8.14.5 50MHz SYSCLKOUT 上的闪存参数：
      6. 8.14.6 40MHz SYSCLKOUT 上的闪存参数：
      7. 8.14.7 闪存编程/擦除时间
      8. 8.14.8 闪存 / OTP 访问时序
      9. 8.14.9 Flash Data Retention Duration
  9. 9 详细说明
    1. 9.1 Overview
      1. 9.1.1  CPU
      2. 9.1.2  Memory Bus (Harvard Bus Architecture)
      3. 9.1.3  外设总线
      4. 9.1.4  Real-Time JTAG and Analysis
      5. 9.1.5  Flash
      6. 9.1.6  M0，M1 SARAM
      7. 9.1.7  L0 SARAM
      8. 9.1.8  Boot ROM
        1. 9.1.8.1 仿真引导
        2. 9.1.8.2 GetMode
        3. 9.1.8.3 引导加载器使用的外设引脚
      9. 9.1.9  Security
      10. 9.1.10 外设中断扩展 (PIE) 块
      11. 9.1.11 外部中断 (XINT1-XINT3)
      12. 9.1.12 内部零引脚振荡器、振荡器和 PLL
      13. 9.1.13 看门狗
      14. 9.1.14 Peripheral Clocking
      15. 9.1.15 Low-power Modes
      16. 9.1.16 外设帧 0，1，2 (PFn)
      17. 9.1.17 通用输入/输出 (GPIO) 复用器
      18. 9.1.18 32 位 CPU 定时器 (0，1，2)
      19. 9.1.19 Control Peripherals
      20. 9.1.20 串行端口外设
    2. 9.2 Memory Maps
    3. 9.3 Register Maps
    4. 9.4 Device Emulation Registers
    5. 9.5 VREG/BOR/POR
      1. 9.5.1 片载电压稳压器 (VREG)
        1. 9.5.1.1 使用片上 VREG
        2. 9.5.1.2 禁用片载 VREG
      2. 9.5.2 On-chip Power-On Reset (POR) and Brown-Out Reset (BOR) Circuit
    6. 9.6 系统控制
      1. 9.6.1 内部零引脚振荡器
      2. 9.6.2 Crystal Oscillator Option
      3. 9.6.3 PLL-Based Clock Module
      4. 9.6.4 输入时钟的损耗（NMI 看门狗功能）
      5. 9.6.5 CPU 看门狗模块
    7. 9.7 Low-power Modes Block
    8. 9.8 Interrupts
      1. 9.8.1 External Interrupts
        1. 9.8.1.1 外部中断电子数据/定时
          1. 9.8.1.1.1 External Interrupt Timing Requirements
          2. 9.8.1.1.2 External Interrupt Switching Characteristics
    9. 9.9 外设
      1. 9.9.1  Analog Block
        1. 9.9.1.1 模数转换器 (ADC)
          1. 9.9.1.1.1 特性
          2. 9.9.1.1.2 ADC 转换开始电子数据/定时
            1. 9.9.1.1.2.1 外部 ADC 转换启动开关特性
          3. 9.9.1.1.3 片载模数转换器 (ADC) 电子数据/定时
            1. 9.9.1.1.3.1 ADC Electrical Characteristics
            2. 9.9.1.1.3.2 ADC 电源模式
            3. 9.9.1.1.3.3 内部温度传感器
              1. 9.9.1.1.3.3.1 Temperature Sensor Coefficient
            4. 9.9.1.1.3.4 ADC 加电控制位时序
              1. 9.9.1.1.3.4.1 ADC 加电延迟
            5. 9.9.1.1.3.5 ADC 顺序模式时序和同步模式时序
        2. 9.9.1.2 ADC 多路复用器
        3. 9.9.1.3 比较器块
          1. 9.9.1.3.1 片载比较器 / DAC 电子数据/定时
            1. 9.9.1.3.1.1 Electrical Characteristics of the Comparator/DAC
      2. 9.9.2  详细说明
      3. 9.9.3  Serial Peripheral Interface (SPI) Module
        1. 9.9.3.1 SPI 主模式电气数据/时序
          1. 9.9.3.1.1 SPI Master Mode External Timing (Clock Phase = 0)
          2. 9.9.3.1.2 SPI Master Mode External Timing (Clock Phase = 1)
        2. 9.9.3.2 SPI 从模式电气数据/时序
          1. 9.9.3.2.1 SPI Slave Mode External Timing (Clock Phase = 0)
          2. 9.9.3.2.2 SPI Slave Mode External Timing (Clock Phase = 1)
      4. 9.9.4  Serial Communications Interface (SCI) Module
      5. 9.9.5  Inter-Integrated Circuit (I2C)
        1. 9.9.5.1 I2C 电气数据/时序
          1. 9.9.5.1.1 I2C 时序要求
          2. 9.9.5.1.2 I2C 开关特性
      6. 9.9.6  Enhanced PWM Modules (ePWM1/2/3/4)
        1. 9.9.6.1 ePWM 电气数据/时序
          1. 9.9.6.1.1 ePWM Timing Requirements
          2. 9.9.6.1.2 ePWM 开关特性
        2. 9.9.6.2 触发区输入时序
          1. 9.9.6.2.1 Trip-Zone Input Timing Requirements
      7. 9.9.7  High-Resolution PWM (HRPWM)
        1. 9.9.7.1 HRPWM 电气数据/时序
          1. 9.9.7.1.1 SYSCLKOUT = 50MHz–60MHz 下的高分辨率 PWM 特性
      8. 9.9.8  Enhanced Capture Module (eCAP1)
        1. 9.9.8.1 eCAP 电气数据/时序
          1. 9.9.8.1.1 Enhanced Capture (eCAP) Timing Requirement
          2. 9.9.8.1.2 eCAP 开关特性
      9. 9.9.9  JTAG 端口
      10. 9.9.10 General-Purpose Input/Output (GPIO) MUX
        1. 9.9.10.1 GPIO 电气数据/时序
          1. 9.9.10.1.1 GPIO - 输出时序
            1. 9.9.10.1.1.1 通用输出开关特性
          2. 9.9.10.1.2 GPIO - 输入时序
            1. 9.9.10.1.2.1 通用输入时序要求
          3. 9.9.10.1.3 针对输入信号的采样窗口宽度
          4. 9.9.10.1.4 低功耗唤醒时序
            1. 9.9.10.1.4.1 IDLE Mode Timing Requirements
            2. 9.9.10.1.4.2 IDLE Mode Switching Characteristics
            3. 9.9.10.1.4.3 待机模式时序要求
            4. 9.9.10.1.4.4 待机模式开关特性
            5. 9.9.10.1.4.5 HALT Mode Timing Requirements
            6. 9.9.10.1.4.6 停机模式开关特性
  10. 10应用、实施和布局
    1. 10.1 TI 参考设计
  11. 11器件和文档支持
    1. 11.1 Device and Development Support Tool Nomenclature
    2. 11.2 Tools and Software
    3. 11.3 文档支持
    4. 11.4 支持资源
    5. 11.5 商标
    6. 11.6 静电放电警告
    7. 11.7 术语表
  12. 12机械、封装和可订购信息
    1. 12.1 封装信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

9.9.10 General-Purpose Input/Output (GPIO) MUX

The GPIO MUX can multiplex up to three independent peripheral signals on a single GPIO pin in addition to providing individual pin bit-banging I/O capability.

The device supports 22 GPIO pins. The GPIO control and data registers are mapped to Peripheral Frame 1 to enable 32-bit operations on the registers (along with 16-bit operations). Table 9-29 shows the GPIO register mapping.

Table 9-29 GPIO Registers
NAMEADDRESSSIZE (x16)DESCRIPTION
GPIO CONTROL REGISTERS (EALLOW PROTECTED)
GPACTRL0x6F802GPIO A Control Register (GPIO0 to 31)
GPAQSEL10x6F822GPIO A Qualifier Select 1 Register (GPIO0 to 15)
GPAQSEL20x6F842GPIO A Qualifier Select 2 Register (GPIO16 to 31)
GPAMUX10x6F862GPIO A MUX 1 Register (GPIO0 to 15)
GPAMUX20x6F882GPIO A MUX 2 Register (GPIO16 to 31)
GPADIR0x6F8A2GPIO A Direction Register (GPIO0 to 31)
GPAPUD0x6F8C2GPIO A Pullup Disable Register (GPIO0 to 31)
GPBCTRL0x6F902GPIO B Control Register (GPIO32 to 38)
GPBQSEL10x6F922GPIO B Qualifier Select 1 Register (GPIO32 to 38)
GPBMUX10x6F962GPIO B MUX 1 Register (GPIO32 to 38)
GPBDIR0x6F9A2GPIO B Direction Register (GPIO32 to 38)
GPBPUD0x6F9C2GPIO B Pullup Disable Register (GPIO32 to 38)
AIOMUX10x6FB62Analog, I/O mux 1 register (AIO0 to AIO15)
AIODIR0x6FBA2Analog, I/O Direction Register (AIO0 to AIO15)
GPIO DATA REGISTERS (NOT EALLOW PROTECTED)
GPADAT0x6FC02GPIO A Data Register (GPIO0 to 31)
GPASET0x6FC22GPIO A Data Set Register (GPIO0 to 31)
GPACLEAR0x6FC42GPIO A Data Clear Register (GPIO0 to 31)
GPATOGGLE0x6FC62GPIO A Data Toggle Register (GPIO0 to 31)
GPBDAT0x6FC82GPIO B Data Register (GPIO32 to 38)
GPBSET0x6FCA2GPIO B Data Set Register (GPIO32 to 38)
GPBCLEAR0x6FCC2GPIO B Data Clear Register (GPIO32 to 38)
GPBTOGGLE0x6FCE2GPIO B Data Toggle Register (GPIO32 to 38)
AIODAT0x6FD82Analog I/O Data Register (AIO0 to AIO15)
AIOSET0x6FDA2Analog I/O Data Set Register (AIO0 to AIO15)
AIOCLEAR0x6FDC2Analog I/O Data Clear Register (AIO0 to AIO15)
AIOTOGGLE0x6FDE2Analog I/O Data Toggle Register (AIO0 to AIO15)
GPIO INTERRUPT AND LOW-POWER MODES SELECT REGISTERS (EALLOW PROTECTED)
GPIOXINT1SEL0x6FE01XINT1 GPIO Input Select Register (GPIO0 to 31)
GPIOXINT2SEL0x6FE11XINT2 GPIO Input Select Register (GPIO0 to 31)
GPIOXINT3SEL0x6FE21XINT3 GPIO Input Select Register (GPIO0 to 31)
GPIOLPMSEL0x6FE82LPM GPIO Select Register (GPIO0 to 31)
Note:

There is a two-SYSCLKOUT cycle delay from when the write to the GPxMUXn/AIOMUXn and GPxQSELn registers occurs to when the action is valid.

Table 9-30 GPIOA MUX
DEFAULT AT RESET
PRIMARY I/O FUNCTION(1)(2)		PERIPHERAL
SELECTION 1		PERIPHERAL
SELECTION 2		PERIPHERAL
SELECTION 3
GPAMUX1 REGISTER BITS(GPAMUX1 BITS = 00)(GPAMUX1 BITS = 01)(GPAMUX1 BITS = 10)(GPAMUX1 BITS = 11)
1-0GPIO0EPWM1A (O)ReservedReserved
3-2GPIO1EPWM1B (O)ReservedCOMP1OUT (O)
5-4GPIO2EPWM2A (O)ReservedReserved
7-6GPIO3EPWM2B (O)ReservedCOMP2OUT(3) (O)
9-8GPIO4EPWM3A (O)ReservedReserved
11-10GPIO5EPWM3B (O)ReservedECAP1 (I/O)
13-12GPIO6EPWM4A (O)EPWMSYNCI (I)EPWMSYNCO (O)
15-14GPIO7EPWM4B (O)SCIRXDA (I)Reserved
17-16ReservedReservedReservedReserved
19-18ReservedReservedReservedReserved
21-20ReservedReservedReservedReserved
23-22ReservedReservedReservedReserved
25-24GPIO12TZ1 (I)SCITXDA (O)Reserved
27-26ReservedReservedReservedReserved
29-28ReservedReservedReservedReserved
31-30ReservedReservedReservedReserved
GPAMUX2 REGISTER BITS(GPAMUX2 BITS = 00)(GPAMUX2 BITS = 01)(GPAMUX2 BITS = 10)(GPAMUX2 BITS = 11)
1-0GPIO16SPISIMOA (I/O)ReservedTZ2 (I)
3-2GPIO17SPISOMIA (I/O)ReservedTZ3 (I)
5-4GPIO18SPICLKA (I/O)SCITXDA (O)XCLKOUT (O)
7-6GPIO19/XCLKINSPISTEA (I/O)SCIRXDA (I)ECAP1 (I/O)
9-8ReservedReservedReservedReserved
11-10ReservedReservedReservedReserved
13-12ReservedReservedReservedReserved
15-14ReservedReservedReservedReserved
17-16ReservedReservedReservedReserved
19-18ReservedReservedReservedReserved
21-20ReservedReservedReservedReserved
23-22ReservedReservedReservedReserved
25-24GPIO28SCIRXDA (I)SDAA (I/OD)TZ2 (I)
27-26GPIO29SCITXDA (O)SCLA (I/OD)TZ3 (I)
29-28ReservedReservedReservedReserved
31-30ReservedReserved var tempcontentStr='/Analog & Mixed-Signal/microcontrollers (mcus) & processors/c2000 real-time microcontrollers'; var partNum ='TMS320F28022-Q1'; var contentStr = replaceSplChars( tempcontentStr )+ "/"+ partNum; var tiContentGroup = contentStr.replace("'",""); function replaceSplChars(content){ var myRegExp=new RegExp("™|®|™","gi"); content=content.replace(myRegExp,""); return content; } var tiProductPathID='/4/5014/'; var tiPageName = 'Literature reader-ZHCSA13P-zh_CN'; var tiDocType = 'Data Sheet'; var tiLibraryStore = new com.TI.tiLibrary.tiLibraryStore(); var tiLibraryViewerStore = tiLibraryStore.viewer_store; RiotControl.addStore(tiLibraryStore); var subRoutes = riot.route.create(); subRoutes("/document-viewer/*/datasheet/*\\?*#*", function(gpn, url, params, anchor) { RiotControl.trigger("ti_library_open_viewer", { document: tiLibraryViewerStore.document, documentLocale: tiLibraryViewerStore.documentLocale, url: "/document-viewer/" + gpn + "/datasheet/" + url + "#" + anchor, toc: true, set_content: true }); }); subRoutes("/document-viewer/*/datasheet/*#*", function(gpn, url, anchor) { RiotControl.trigger("ti_library_open_viewer", { document: tiLibraryViewerStore.document, documentLocale: tiLibraryViewerStore.documentLocale, url: "/document-viewer/" + gpn + "/datasheet/" + url + "#" + anchor, toc: true, set_content: true }); }); subRoutes("/document-viewer/*/datasheet/*", function(gpn, url) { RiotControl.trigger("ti_library_open_viewer", { document: tiLibraryViewerStore.document, documentLocale: tiLibraryViewerStore.documentLocale, url: "/document-viewer/" + gpn + "/datasheet/" + url, toc: true, set_content: true }); }); subRoutes("/document-viewer/*/*/datasheet/*\\?*#*", function(locale, gpn, url, params, anchor) { RiotControl.trigger("ti_library_open_viewer", { document: tiLibraryViewerStore.document, documentLocale: tiLibraryViewerStore.documentLocale, url: "/document-viewer/" + locale + "/" + gpn + "/datasheet/" + url + "#" + anchor, toc: true, set_content: true }); }); subRoutes("/document-viewer/*/*/datasheet/*#*", function(locale, gpn, url, anchor) { RiotControl.trigger("ti_library_open_viewer", { document: tiLibraryViewerStore.document, documentLocale: tiLibraryViewerStore.documentLocale, url: "/document-viewer/" + locale + "/" + gpn + "/datasheet/" + url + "#" + anchor, toc: true, set_content: true }); }); subRoutes("/document-viewer/*/*/datasheet/*", function(locale, gpn, url) { RiotControl.trigger("ti_library_open_viewer", { document: tiLibraryViewerStore.document, documentLocale: tiLibraryViewerStore.documentLocale, url: "/document-viewer/" + locale + "/" + gpn + "/datasheet/" + url, toc: true, set_content: true }); }); subRoutes("/document-viewer/*/datasheet#*/*", function(gpn, url, fragment) { RiotControl.trigger("ti_library_open_viewer", { document: tiLibraryViewerStore.document, documentLocale: tiLibraryViewerStore.documentLocale, url: "/document-viewer/" + gpn + "/datasheet#" + url + "/" + fragment, toc: true, set_content: true }); }); subRoutes("/document-viewer/*/*/datasheet#*/*", function(locale, gpn, url, fragment) { RiotControl.trigger("ti_library_open_viewer", { document: tiLibraryViewerStore.document, documentLocale: tiLibraryViewerStore.documentLocale, url: "/document-viewer/" + locale + "/" + gpn + "/datasheet#" + url + "/" + fragment, toc: true, set_content: true }); }); subRoutes("/document-viewer/lit/html/*", function(litnum) { RiotControl.trigger("ti_library_open_viewer", { document: tiLibraryViewerStore.document, documentLocale: tiLibraryViewerStore.documentLocale, url: "/document-viewer/lit/html/" + litnum, toc: true, set_content: true }); }); subRoutes("/document-viewer/lit/html/*/*\\?*#*", function(litnum, url, params, anchor) { RiotControl.trigger("ti_library_open_viewer", { document: tiLibraryViewerStore.document, documentLocale: tiLibraryViewerStore.documentLocale, url: "/document-viewer/lit/html/" + litnum + "/" + url + "#" + anchor, toc: true, set_content: true }); }); subRoutes("/document-viewer/lit/html/*/*#*", function(litnum, url, anchor) { RiotControl.trigger("ti_library_open_viewer", { document: tiLibraryViewerStore.document, documentLocale: tiLibraryViewerStore.documentLocale, url: "/document-viewer/lit/html/" + litnum + "/" + url + "#" + anchor, toc: true, set_content: true }); }); subRoutes("/document-viewer/lit/html/*#*/*", function(litnum, url, anchor) { RiotControl.trigger("ti_library_open_viewer", { document: tiLibraryViewerStore.document, documentLocale: tiLibraryViewerStore.documentLocale, url: "/document-viewer/lit/html/" + litnum + "#" + url + "/" + anchor, toc: true, set_content: true }); }); subRoutes("/document-viewer/*/lit/html/*#*/*", function(locale, litnum, url, anchor) { RiotControl.trigger("ti_library_open_viewer", { document: tiLibraryViewerStore.document, documentLocale: tiLibraryViewerStore.documentLocale, url: "/document-viewer/" + locale + "/lit/html/" + litnum + "#" + url + "/" + anchor, toc: true, set_content: true }); }); subRoutes("/document-viewer/lit/html/*/*", function(litnum, url) { RiotControl.trigger("ti_library_open_viewer", { document: tiLibraryViewerStore.document, documentLocale: tiLibraryViewerStore.documentLocale, url: "/document-viewer/lit/html/" + litnum + "/" + url, toc: true, set_content: true }); }); subRoutes("/document-viewer/*/lit/html/*/*\\?*#*", function(locale, litnum, url, params, anchor) { RiotControl.trigger("ti_library_open_viewer", { document: tiLibraryViewerStore.document, documentLocale: tiLibraryViewerStore.documentLocale, url: "/document-viewer/" + locale + "/lit/html/" + litnum + "/" + url + "#" + anchor, toc: true, set_content: true }); }); subRoutes("/document-viewer/*/lit/html/*/*#*", function(locale, litnum, url, anchor) { RiotControl.trigger("ti_library_open_viewer", { document: tiLibraryViewerStore.document, documentLocale: tiLibraryViewerStore.documentLocale, url: "/document-viewer/" + locale + "/lit/html/" + litnum + "/" + url + "#" + anchor, toc: true, set_content: true }); }); subRoutes("/document-viewer/*/lit/html/*/*", function(locale, litnum, url) { RiotControl.trigger("ti_library_open_viewer", { document: tiLibraryViewerStore.document, documentLocale: tiLibraryViewerStore.documentLocale, url: "/document-viewer/" + locale + "/lit/html/" + litnum + "/" + url, toc: true, set_content: true }); }); var compose_url = function(q) { //URL format: scheme:[//[user[:password]@]host[:port]][/path][?query][#fragment] var tempUrl = q.url.replace("//www.yogichopra.com/", ""); var url = tempUrl.replace("//www.yogichopra.com/", ""); if (q.search != null) { var params = ""; var hash = ""; var url_parts = url.split('#'); if (url_parts.length == 2) { url = url_parts[0]; hash = url_parts[1]; } var param_parts = url.split('?'); if (param_parts.length == 2) { url = param_parts[0]; var parsed_params = param_parts[1].split('&'); var keyword_param_found = false; for (var i = 0; i < parsed_params.length; i++) { if (parsed_params[i].indexOf('search=') == 0) { keyword_param_found = true; parsed_params[i] = 'search=' + q.search; } } if (!keyword_param_found) { parsed_params.push('search=' + q.search); } params = parsed_params.join('&'); } else { params = 'search=' + q.search; } if (params > "") { url = url + '?' + params; } if (hash > "") { url = url + '#' + hash; } } return url; }; tiLibraryViewerStore.compose_url_route = function(location, q) { return compose_url(q); }; tiLibraryViewerStore.compute_content_href = function(href, url) { return url; }; tiLibraryViewerStore.compose_topic_url = function(location, q) { return compose_url(q); }; tiLibraryViewerStore.important_notice_url = "//www.yogichopra.com/document-viewer/cn/TMS320F28022-Q1/datasheet/important_notice#ImpNotice001"; var ods_reader = riot.mount('ti-library-viewer', { store: tiLibraryStore.list_store, viewerstore: tiLibraryViewerStore }); riot.route.base('/'); riot.route.start(true); compute_document_locale = function(docName) { var locale = 'en_US'; if (docName) { if (docName.toLowerCase().indexOf('z')===0) { locale = 'zh_CN'; } else if (docName.toLowerCase().indexOf('j') == 0) { locale = 'ja_JP'; } } return locale; } open_reader = function() { var path = window.location.pathname.split('/'); var path_minus_filename = ''; for (var i = 0; i < path.length - 1; i++) { if (i == 0 && path[i] == '') { console.log("double slashes found in beginning of document path; treating document path as local machine path"); continue; } path_minus_filename += "/" + path[i]; } RiotControl.trigger("ti_library_open_viewer", { documentLocale: compute_document_locale( "ZHCSA13P"), document: { href: path_minus_filename, lit_num: "ZHCSA13P", doc_type: "Data Sheet", show_toc: "true", translated_doc_type: "数据表", gpn: "TMS320F28022-Q1", title: "TMS320F2802x 微控制器", disclaimer: "本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。 ", product: "//www.yogichopra.com/product/cn/TMS320F28022-Q1", email: 'mailto:?subject=TMS320F28022-Q1 Datasheet&body=/document-viewer/cn/TMS320F28022-Q1/datasheet', download: '//www.yogichopra.com/cn/lit/gpn/TMS320F28022-Q1', tistore: '//store.ti.com/Search.aspx?k=TMS320F28022-Q1&pt=-1', productstatusdescription: 'PRODUCTION DATA' }, url: "/document-viewer/cn/TMS320F28022-Q1/datasheet/GUID-2D61688E-BBA2-4682-A9C5-3BEB3F650E47", prepopulated: true, modalOptions: { dismissible: false } }); } open_reader();
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